Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-12-13
1998-08-11
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395309, 395310, 395306, 39520001, 395840, 395856, 711163, G06F 1300, G06F 1314
Patent
active
057940690
ABSTRACT:
An information handling system transfers data blocks between a host processing side having a CPU and a host memory and a local processing side having a local processing unit and a local memory. The local memory includes a DCB queue memory portion having a plurality of DCB images each image defining host and local addresses of a corresponding data transfer. The DCB images also store a default status condition representing the most likely condition of a data transfer which in the preferred embodiment is a no error condition. A data transfer status detector determines whether the default status condition is true or false. If true, the default status information relating to a corresponding data block transfer is posted on the host processing side without local processing unit intervention.
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Chisholm Douglas Roderick
Hoch Gary
Lee Timothy Vincent
McNeill, Jr. Andrew Boyce
Wachtel Ed
Chan Eddie P.
International Business Machines Corp.
Kim Hong C.
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