Information block transfer management in a multiprocessor comput

Details Information block transfer management in a multiprocessor comput Information block transfer management in a multiprocessor comput

1996-12-18

1999-12-21

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711 3, 711118, 711119, 711121, 711122, 711123, 711126, 711128, 711135, 36518902, 36518905, 36523003, 395293, 395280, 395308, 395872, 395871, G06F 1200

Patent

active

060063092

ABSTRACT:
A computer system including a group of CPUs, each having a private cache which communicates with its CPU to receive requests for information blocks and for servicing such requests includes a CPU bus coupled to all the private caches and to a shared cache. Each private cache includes a cache memory and a cache controller including pairs of half-block operand buffers, each divided into quarter block segments. The operand buffer set is coupled to selectively receive, under control of an input multiplexer, requested information blocks from the CPU bus in quarter-block segments and is further coupled to selectively send, under control of an output multiplexer, received quarter-block segments to the CPU and received full blocks to the cache memory.

REFERENCES:
patent: 4471429 (1984-09-01), Poter et al.
patent: 5398325 (1995-03-01), Chang et al.
patent: 5423016 (1995-06-01), Tsuchiya et al.
patent: 5678020 (1997-10-01), Singh et al.
patent: 5737573 (1998-04-01), Funaki et al.

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