Inexpensive wafer level MMIC chip packaging

Details Inexpensive wafer level MMIC chip packaging Inexpensive wafer level MMIC chip packaging

2005-05-03

2005-05-03

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S775000, C257S750000, C257S758000, C257S759000

Reexamination Certificate

active

06888253

ABSTRACT:
An inexpensive package for a semiconductor chip (1) that incorporates a stress relief buffer (13) between a side of the chip and the metal carrier layer (2) to absorb thermally induced stress produced by significantly different rates of thermal expansion of the wafer and the metal carrier. The buffer (13) is formed by a polymer that is flexible and can be etched, contains a coefficient of thermal expansion that does not significantly differ from that of the chip and/or a combination of CET and elasticity that retains a physical connection with the side of the chip and the metal carrier over the temperature range of operation anticipated for the chip. Polyimide or paraylene are preferred examples. Vias (15) extend through the buffer to place the metal carrier electrically in common with the metal layer (5) found on the back surface of the wafer so that an electrical ground applied to the metal carrier layer (2) may extend through to that surface.

REFERENCES:
patent: 5229647 (1993-07-01), Gnadinger
patent: 6002180 (1999-12-01), Akram et al.
patent: 6075712 (2000-06-01), McMahon
patent: 6300688 (2001-10-01), Wong
patent: 6362528 (2002-03-01), Anand

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