Inductor-tuned buffer circuit with improved modeling and design

Details Inductor-tuned buffer circuit with improved modeling and design Inductor-tuned buffer circuit with improved modeling and design

2008-07-15

2008-07-15

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000, C326S080000, C326S115000

Reexamination Certificate

active

11507896

ABSTRACT:
According to one exemplary embodiment, an inductor-tuned buffer circuit includes at least one input transistor for receiving a time varying input signal, where the at least one input transistor drives an output of the buffer circuit. The buffer circuit further includes a buffer inductor coupled to the output of the buffer circuit. The buffer circuit is utilized to drive a capacitive load through an interconnecting conductor, where the buffer inductor is situated in proximity to the capacitive load so as to cause a parasitic inductance of the interconnecting conductor to be less than, or much less than, the buffer inductor.

REFERENCES:
patent: 6340899 (2002-01-01), Green
patent: 6650163 (2003-11-01), Burns et al.
patent: 7126403 (2006-10-01), Kenney et al.
patent: 7190232 (2007-03-01), Teo
patent: 2002/0017921 (2002-02-01), Green

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