Individually adjustable back-bias technique

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Reexamination Certificate

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06858897

ABSTRACT:
An individual-well adaptive method of body bias control that mitigates the effects of D2D and WD process variations is shown. It is assumed that p-type transistors are grouped in sections. The bodies of all the p-type transistors within a section are connected to a single n-well. This section size can be small enough to provide fine-granular adjustments to the circuit without having any impact on area overhead. With a small amount of additional circuitry and routing, individual well biases can be intelligently adjusted resulting in closely controlled chip power and performance. Experimental results show that binning yields as low as 17% can be improved to greater than 90% using the proposed method.

REFERENCES:
patent: 5844425 (1998-12-01), Nguyen et al.
patent: 6326832 (2001-12-01), Macaluso
patent: RE38222 (2003-08-01), Wu
H.C. Wann et al., “Channel Doping Engineering of MOSFET with Adaptable Threshold Voltage Using Body Effect for Low Voltage and Low Power Applications”, 1995 International Symposium on VLSI Technology, Systems, and Applications, pp. 159-163, 1995.
T. Kuroda et al, “A 0.9V 150MHz 10-mW 2-D Discrete Cosine Transform Core Processor With Variable Threshold-Voltage Scheme”, 1996 ISSCC Digest of Technical Papers, pp. 166-167, 1996.
M. Miyazaki et al, “1.2-GIPS/W Microprocessor Using Speed Adaptive Threshold-V Itage CMOS With Forward Bias”, IEEE Journal of Solid-State Circuits, vol. 37, No. 2, pp. 210-217, F b. 2002.
M. Miyazaki et al, “A Delay Distribution Squeezing Scheme With Speed-Adaptive Threshold-Voltage CMOS (SA-Vt CMOS) for Low Voltage LSIs”, Proceedings of 1998 International Symposium on Low Power Electronics and Design, pp. 48-53, Aug. 1998.
James Tschanz et al., “Adaptive body bias for reducing impacts of die-to-die within-die parameter variations on microprocessor requency and leakage”, IEEE ISSCC 25.7, pp. 422-423, 478-479, Feb. 2002.

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