Individual memory page activity timing method and system

Details Individual memory page activity timing method and system Individual memory page activity timing method and system

2002-04-05

2004-02-03

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189050, C365S189120, C365S194000

Reexamination Certificate

active

06687172

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to electronic circuitry and, more particularly, to timer circuits for use with memories.
BACKGROUND
Memory controller circuits can be used in a variety of computer systems (e.g., desktop personal computers, notebook computers, personal digital assistants, etc.) to facilitate the computer system's processor in accessing memory chips. These memory chips generally include the main memory of the computer system, which typically includes several dynamic random access memory (DRAM) chips. DRAM chips include, for example, synchronous DRAM (SDRAM), extended data out (EDO) DRAM, Rambus (R)DRAM, DDR (double data rate) and DRAM chips. The memory controller provides a memory interface for connecting to one or more of such DRAM chips, and a system interface to connect to the system processor(s). The memory controller uses these interfaces to route data between the processor and the DRAM chips using appropriate address, control and data signals.
Generally, the DRAM chips used in modern computers are organized in groups and mounted on one or more “memory modules.” Common memory modules in use today are known as DIMMs (Dual In-line Memory Modules) that typically include one or more DRAM chips mounted on a small circuit board.
Typically, a modern DIMM can store 32, 64, 128, 256, and 512 megabytes (Mb) of memory, which corresponds to the total memory capacity of the memory chips on the DIMM. The memory on each DRAM chip is logically arranged into a memory array of several rows and columns of memory “cells.” Each memory cell has a particular address, and stores a single bit of data. This memory array is then logically partitioned into one or more “banks” of memory. In modern DRAM chips, memory is accessed on a “page” basis, wherein the memory cells for a given row within a bank form a “page” of memory.
Accessing DRAM is generally a multi-step process that is performed by the memory controller in the following manner. First, the page(s) corresponding to the requested data or instructions are identified. Once the page(s) are known, the appropriate bank corresponding to the page(s) is/are determined. Generally, the particular page(s) of data requested will initially be in one of three states: page hit, page empty, or page miss. If the state is a page hit, a desired page is already loaded into a bank of sense amplifiers (amps) corresponding to the memory bank the page is stored in. If the state is a page empty, data corresponding to the desired page will need to be loaded into an appropriate sense amp bank via an “activate” command before it can be accessed. If the state is a page miss, the specified bank contains a different page of data than that requested. This existing page will first be required to be “closed,” which includes writing it back to the DRAM memory array using a “precharge” command, and then loading the appropriate page into the sense amp bank using the activate command.
The foregoing three states have an impact on access latency. A page hit state means the page is ready to be accessed with no additional latency. A page empty state requires an activate command, while a page miss requires both pre-charge and activate commands, each of which may take one or more clock cycles. The actual penalty (i.e., delay) for each type of access will depend on the memory technology, memory organization and architecture, and on other rules specific to each memory technology. The general rule however is that a page hit is fastest, and a page empty is slower, and a page miss is slowest. Also, keeping a page open dissipates power. Thus, from a power standpoint it may be desirable to close pages sooner rather than later.
Some existing page-management policies include timer mechanisms. With timer mechanisms, “idle” timers are used to determine that memory in general, or a specific bank in particular, have been idle for some predetermined number X clock cycles. If X clock cycles have transpired with no accesses, the page(s) is/are closed. The counters may be per bank, in which case only that bank's pages will be closed when the timer expires, but such mechanisms would require a large number of timers in DIMMs with a large number of banks. Each timer occupies area and dissipates power and, thus, a large number of timers may be undesirable in some applications. Other implementations may have a timer per DIMM or a timer for all of the system memory. In such implementations, all pages in a DIMM or all of the system memory may be closed when the timer expires. However, such timer mechanisms provide relatively coarse page management.


REFERENCES:
patent: 5386383 (1995-01-01), Raghavachari
patent: 5473572 (1995-12-01), Margeson, III
patent: 5848022 (1998-12-01), Jiang
patent: 6111812 (2000-08-01), Gans et al.
patent: 6233661 (2001-05-01), Jones et al.
patent: 6269433 (2001-07-01), Jones et al.
patent: 6304502 (2001-10-01), Watanabe et al.
patent: 6389520 (2002-05-01), Christenson
patent: 6564284 (2003-05-01), Christenson
Double Data Rate (DDR) SDRAM, Rev. 2/00, pp. 1-67, Microcon Semiconductor Products, Inc., Boise ID, USA.
Cuppu, V., et al., “A Performance Comparison of Contemporary DRAM Architectures”, IEEE, Proceedings of the 26thInternational Symposium on Computer Architecture, May 2-4, 1999, pp. 1-12.
Yamauchi, T., et al., “The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors”, Proceedings of the 17thConference on Advanced Research in VLSI (ARVLSI '97), 17 pages.
Cuppu, et al., “High-Performance DRAMs in Workstation Environments”, IEEE Transactions on Computers, vol. 50, No. 11, Nov. 2001, pp. 1-20.

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