Individual I/O modulation in memory devices

Details Individual I/O modulation in memory devices Individual I/O modulation in memory devices

2008-06-17

2008-06-17

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S189050, C365S230060

Reexamination Certificate

active

07388794

ABSTRACT:
A DRAM circuit with reduced power consumption and in some circumstances faster memory array access speed. Input/output lines connected to a memory array are sensed according to their capacitance/length in comparison to a threshold capacitance/length. The input/output lines that are shorter, or less capacitive, than the threshold are sensed sooner than those input/output lines that are longer, more capacitive, than the threshold. Since shorter input/output lines are sensed sooner, they require less power and may be accessed faster.

REFERENCES:
patent: 5457661 (1995-10-01), Tomita et al.
patent: 5631871 (1997-05-01), Park et al.
patent: 6304509 (2001-10-01), Hirobe et al.
patent: 6359815 (2002-03-01), Sato et al.
patent: 6469540 (2002-10-01), Nakaya

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