Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Bipolar transistor
Reexamination Certificate
2002-12-30
2004-08-03
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Bipolar transistor
C257S200000
Reexamination Certificate
active
06770919
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the growth of an epitaxial layer structure in heterojunction bipolar transistor (HBT) technology. More specifically, the invention employs a double-etch-stop ledge (DESL) structure in the emitter and base junction on an indium phosphide (InP) based HBT.
2. Discussion of the Related Art
In manufacturing three-terminal vertical devices, such as a heterojunction bipolar transistor (HBT), collector, base and emitter layers are successively deposited on a substrate using epitaxial technology. Epitaxial technologies such as metal-organic molecular beam epitaxy (MOMBE), gas-source molecular beam epitaxy (GSMBE), and metal-organic chemical vapor deposition (MOCVD) are well known. Such epitaxial technologies are particularly useful for producing multi-layered structures. The advantages of HBT technology over high-electron mobility field effect transistor (HEMT) technology are simpler multi-layered structures, the ability to integrate directly with optical devices such as p-intrinsic-n (PIN) diodes, better uniformity, less stringent feature-size requirement, smaller chip area, large scale integrability, and hence, a lower fabrication processing cost. Such multi-layered structures employ an InP technology which has become a well-recognized viable technology for next generation high speed long-wavelength optical communication systems. Its applications in optoelectronic integrated circuits (OEIC) include front-end transmitters, receivers, and clock and data recovery (CDR) integrated circuits (ICs).
Indium phosphide systems are preferred over gallium arsenide (GaAs) based HBT material systems because of their higher frequency response due to the faster electron saturation velocity in indium-containing materials such as indium gallium arsenide (InGaAs). The lower surface recombination velocity in InGaAs material is also advantageous when InP HBT devices are scaled down to the submicron regime. Superior high-frequency InP HBT performance with characteristics including a transit frequency, f
T
of over 220 GHz and an oscillation frequency, f
Max
of greater than 400 GHz have been demonstrated using a wet-etching. See for example, Yamahata, S. et al., “Over 220 GHz f
T
and f
Max
InP/InGaAs Double-Heterojunction Bipolar Transistors with a New Hexagonal-Shaped Emitter,” 17
th
Annual GaAs IC Symposium, Tech. Dig., , pp. 163-166, 1995 and Lee, Q. et al., “A >400 GHz f
Max
Transferred-Substrate Heterojunction Bipolar Transistor IC Technology,” IEEE Electron Device Lett., vol. 19, pp. 77-79, 1998.
The problems encountered in InP HBT technologies include the unknown device reliability and the inability to lower noise performance. Various approaches have been used to grow conventional InP HBT structures employing DESL structure. See for example, Bitter, M. et al., “Monolithic InGaAs/InP pin/HBT Optical Receiver Front-End Module for Data rates up to 40-Gb/s,” Indium Phosphide and Related Materials Conference in Davos, Switzerland, p. 31, 1999, Huber, D. et al., “InP-InGaAs Single HBT Technology for Photoreceiver OEICs at 40 Gb/s and Beyond,” J. of Lightwave Technology, vol. 18, no. 7, pp.992-1,000, 2000, and Hafizi, M., “New Submicron HBT IC Technology Demonstrates Ultra-Fast, Low-Power Integrated Circuits,” IEEE Electron Device Lett., vol.45, no. 9, pp. 1862-1868, 1998.
Designers of 40-Gbps systems can select devices manufactured using indium phosphide (InP) heterojunction bipolar transistor (HBT) technology. InP is a promising technology that is growing in popularity due to its RF performance, which is greater than 150 GHz f
T
and f
Max
at moderate to high current densities (50 to 100 kA/cm2). The f
T
is high because of the thin base and collector layers employed in the epitaxial structure of the device. Thinner layers give rise to fast transit times for electrons in the base and collector that in turn enable a high f
T
. Also, scaling of the devices (especially by narrowing the emitter stripe together with heavily doping the base) significantly reduces the value of the base resistance, which in turn leads to high values of f
Max
. As a consequence of its high f
T
and fMax, InP HBT structures can offer performance margin in 40-Gbps transmission systems.
SUMMARY OF THE INVENTION
Accordingly, the present invention is related to InP-based HBTs using a double-etch-stop ledge structure in the emitter-base junction.
An advantage of the present invention is to provide an epitaxial layer structure that may potentially achieve reliable, high speed, and low noise device performance in InP-based HBTs for high data rate receivers and OEICs.
Another advantage of the present invention is to provide an epitaxial layer structure that enables a robust and highly manufacturable wet-etching InP HBT fabrication process using well-known selective etching techniques.
A further advantage of the present invention is to provide minimized surface recombination current at the exposed emitter-base junction, and, hence, maintain the reasonable current gain as the HBT devices are scaled down to the sub-micron regime.
Another advantage of the present invention is that the thin alloy-through emitter layer that is sandwiched between the InGaAs base layer and the n-type InGaAs emitter etch-stop layer can be preserved for base metal alloy-through purposes.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, an indium phosphide heterojunction bipolar transistor layer structure formed on an InP substrate includes: an n+ InGaAs sub-collector; an n+ InP sub-collector; an unintentionally-doped InGaAs collector; a carbon-doped base; an n-type InP emitter; an n-type InGaAs etch-stop layer; an n-type InP emitter; and a InGaAs cap layer.
In another aspect of the invention, a method of making an indium phosphide heterojunction bipolar transistor layer structure on an InP substrate includes forming a first InGaAs layer having a first doping concentration; forming a first InP layer having a first doping concentration; forming a second InGaAs layer; forming a layer doped with carbon having a second doping concentration;
forming a second InP layer having a first doping concentration; forming a third InGaAs layer having a first doping concentration; forming a third InP layer having a first doping concentration; and forming a fourth InGaAs layer.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from that description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
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Shoji Yamahata et al., “Over-220 . . . Double-Heterojunction Bipolar Transistors with a New Hexagonal-Shaped Emitter,” Session E, IEEE 1995, pp. 163-166.
D. Huber et al., “InP-InGaAs Single HBT Technology for Photoreceiver OEIC's at 40 Gb/s and Beyond,” Journal of Lightwave Technology, vol. 18, No. 7, Jul. 2000, pp. 992-1000.
Madjid Hafizi, “New Submicron HBT IC Technology Demonstrates Ultra-Fast, Low-Power Integrated Circuits,” IEEE Transactions On Electron Devices, vol. 45, No. 9, Sep. 1998, pp. 1862-1868.
M. T. Fresina,
Caruth David C.
Chiang Shyh
Feng Milton
Mckenna Long & Aldridge LLP
Wilson Allan R.
Xindium Technologies, Inc.
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