Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1998-09-21
2000-10-03
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 16, 712 11, 709200, 709243, G06F 1500
Patent
active
061287199
ABSTRACT:
An interconnection network used for a multiprocessor system. An indirect n-dimensional rotator graph network having a transmission path of arbitrary nodes in a multiprocessor system including n! nodes includes n! input ports, n! output ports, a first stage switch module including n! demultiplexers, second through (n-1)th stage switch modules each having n! n.times.n crossbar switches, and an nth stage switch module including n! multiplexers, in which the switches or the demultiplexers composing switch modules of first to (n-1)th stages comprise n generators g.sub.1, g.sub.2, . . . , g.sub.n, the g.sub.1 is connected to a switch or multiplexer of a later stage having an identifier identical to that of a demultiplexer or switch, to which the g.sub.1 is included, and the g.sub.i (2.ltoreq.i.ltoreq.n) is connected to a switch or multiplexer of a later stage having an identifier identical to the identifier obtained by rotating the first (n-i+2) symbols of the identifier of the switch or the demultiplexer to which the g.sub.i is included to the left. Accordingly, when the number of nodes is equal in indirect networks, a network according to the present invention, may have the transmission stage shorter than other networks. Thus, the tag required for routing is reduced, to thereby increase a message transmission efficiency rate.
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An Meng-Ai T.
Bushnell Esq. Robert E.
Monestime Mackly
Samsung Electronics Co,. Ltd.
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