Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2000-10-18
2004-05-11
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S002000, C711S165000
Reexamination Certificate
active
06735664
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to devices and methods for accessing registers of memory devices.
2. Description of the Related Art
IEEE Standard 802.3u-1995, section 22.2.4, describes a medium independent interface (MII) management interface for controlling a physical layer device (PHY) and gathering status information from the PHY. The MII management register set includes 16 sixteen-bit vendor-specified memory registers, for a total of 256 bits. The vendor-specified registers may be used to store control parameters used to enhance operation of the PHY.
For complex PHYs, the 256 bits of vendor-specified space in the MII management register set may be inadequate for storing desired information such as numerous control parameters. Accordingly, it would be desirable to have a means of effectively increasing the accessible memory space. Moreover, it will be appreciated that there is a general need for efficiently accessing specific registers or blocks of registers within a memory device.
SUMMARY OF THE INVENTION
A method of indirect addressing involves use of a bank select register and a bank of multiple directly-accessible registers to indirectly access registers of a memory device. Bank select data is written to the bank select register, specifying a bank of registers to be indirectly accessed. Read and/or write operations are then performed, for example, reading data from the specified bank of registers and transferring it to the directly-accessible registers, or writing data to the directly-accessible registers from an external source, and transferring the data to the registers of the specified bank of indirectly-accessible registers.
According to an aspect of the invention, a method of indirect addressing involves performing read and/or write operations between a bank of directly-accessible registers and a specified bank of indirectly-accessible registers. According to a specific embodiment of the invention, the bank of indirectly-accessible registers is specified by placing bank control data in a directly-accessible bank select register.
According to another aspect of the invention, a PHY device has an indirectly-accessible extended memory register set which is operatively coupled to a directly-accessible memory register set. According to a specific embodiment of the invention, the directly-accessible memory register set is an MII management register set which is operatively coupled to an MII.
According to yet another aspect of the invention, a method of performing an operation on indirectly-accessible registers of a memory device includes the steps of: storing bank select information in a directly-accessible bank select register, the bank select information corresponding to a bank of the indirectly-accessible registers; and exchanging data between other directly-accessible registers and the indirectly-accessible registers of the bank.
According to still another aspect of the invention, a method of performing an operation on indirectly-accessible registers of a physical layer device includes the steps of: sending bank select information to the physical layer device via a medium independent interface (MII) of the device; storing the bank select information in a bank select register of an MII management register set of the device; and exchanging data between other registers of the MII management register set, and multiple of the indirectly-accessible registers indicated by the bank select information.
According to a further aspect of the invention, a physical layer device includes a medium independent interface (MII); an indirectly-accessible memory device having multiple banks of registers, each of the banks having multiple registers; and means for selectively accessing one or more of the banks via the MII.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
REFERENCES:
patent: 5734858 (1998-03-01), Patrick et al.
patent: 5890222 (1999-03-01), Agarwal et al.
Frazier, H.M., Jr.; Media Independent Interface: Concepts and Guidelines, WESCON/'95. Conference record, pp 348-353.
Advanced Micro Devices , Inc.
Renner , Otto, Boisselle & Sklar, LLP
Sparks Donald
Truong Bao Q.
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