Indexing a translation lookaside buffer (TLB)

Details Indexing a translation lookaside buffer (TLB) Indexing a translation lookaside buffer (TLB)

2008-10-28

2011-11-22

Nguyen, Hiep (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

Reexamination Certificate

active

08065501

ABSTRACT:
A processor is to comprise a central processing unit (CPU), an address generation unit (AGU), an index generation unit and a translation look-aside buffer (TLB). The CPU of the processor is to generate signal to retrieve instructions from a memory. The AGU is to generate a final linear address and an initial linear address after receiving at least three input source values. An index generation unit coupled to the AGU is to generate a set-index value using the bits of at least the three input source values or the bits of the initial linear address even before the bits of the initial linear address are adjusted for carry. A TLB is to generate a physical address using the final linear address and an entry indexed by the set-index value.

REFERENCES:
patent: 6079005 (2000-06-01), Witt et al.
patent: 6721848 (2004-04-01), Gaither
patent: 7162609 (2007-01-01), Morrow et al.
patent: 7434027 (2008-10-01), Morrow et al.

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