Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-10-24
2000-05-09
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711146, 711141, 711143, 711158, 711144, G06F 1200
Patent
active
060617659
ABSTRACT:
In accordance with the present invention, a method and apparatus is provided for storing victim data evicted from a cache and for satisfying pending requests or probe messages that target victim data, using a set of victim data buffers coupled to a central processing unit of a computer system. Storage locations referred to as a "victim valid bit" and a "probe valid bit" are associated with each victim data buffer in the computer system to indicate a release condition for the coupled victim data buffer. With such an arrangement, the victim data buffer can be deallocated when the victim valid bit and the probe valid bit have both been cleared.
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Doren Stephen Van
Keller James Bernard
Steely, Jr. Simon C.
Stewart Robert Eugene
Chan Eddie P.
Compaq Computer Corporation
Kim Hong
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