Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-05-05
2000-07-25
Wright, Norman M.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 9, H02H 305
Patent
active
060947284
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to disk array system and disk array controller having an architecture such as RAID5.
BACKGROUND ART
In a prior art disk array controller architecture, one internal bus is used or two buses, that is, a control bus by a built-in MPU and a user data transfer bus between a host interface and a disk device interface are used.
Further, as disclosed in JP-A-6-180623, a dedicated circuit such as a FIFO (First-in First-out) for speed control is needed between the host interface and the disk device. In the prior art, in order to fully derive the transfer performance of the host interface and the drive without causing a performance neck by an internal bus of the array controller, it is necessary to increase the transfer rate of the internal bus to a sufficiently high rate as compared with the transfer rate of the host interface and the drive interface, and a dedicated circuit such as FIFO are required between the high speed internal bus and the host interface and the drive interface, and in a disk array controller having a plurality of channels of host interface and disk device interface, this is a factor of high cost of the disk array controller and the disk array system.
DISCLOSURE OF INVENTION
It is an object of the present invention to provide disk array controller and disk array system which solve the above problems and increases the data transfer rate with a low cost.
It is another object of the present invention to provide a disk array controller and disk array system which reduce a traffic to a memory (disk cache) to improve an effective transfer rate.
It is other object of the present invention to provide disk array controller and disk array system which allow the data scattering/gathering and the parity data generation.
In order to achieve the above objects, the present invention provides a disk array controller or a disk array system which is controller characterized by the provision of a disk array control unit having one or more MPUs; and the provision of a user data transfer unit having a host interface with a host computer, a memory (disk cache) for temporarily storing data, redundant data generation means (REDUNDANT DATA GENERATOR) for generating redundant data, a multi-channel disk device interface and data transfer control means having one or more channels for controlling the data transfer between the host interface, the memory, the redundant data generation means and the disk device interface; and that a control bus (MPU bus) for controlling the disk device interface, the redundant data generation means and the data transfer control means of the user data transfer control unit by the disk array control unit, a host data bus for conducting the data transfer between the host interface and the memory by the data transfer control means in the user data transfer control unit and a drive data bus for conducting the data transfer between the disk device interface and the memory by the data transfer control means in the user data transfer control unit are provided.
The present invention is further characterized by that, in the disk array controller or the disk array system, the host interface and the disk device interface comprise SCSI (Small Computer System Interface) interfaces such as SCSI-2.
The present invention is further characterized by that in the disk array controller or the disk array system, the data transfer control means allows the designation of a plurality of data transfer paths between areas of the memory and the disk device interface.
The present invention is further characterized by that, in the disk array controller or the disk array system, the data transfer means comprises a plurality of counters for designating addresses of the memory and a plurality of registers for designating channels of the disk device interface corresponding to the respective counters.
The present invention is further characterized by that, in the disk array controller or the disk array system, the data transfer means transfers data between the areas of the me
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Honda Kiyoshi
Ichikawa Masatoshi
Isono Soichi
Matsumoto Jun
Hitachi , Ltd.
Wright Norman M.
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