Independent chip select for SRAM and DRAM in a multi-port RAM

Details Independent chip select for SRAM and DRAM in a multi-port RAM Independent chip select for SRAM and DRAM in a multi-port RAM

1998-01-23

2000-12-05

Robertson, David L.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711104, 711149, 711130, 711131, 36523003, G06F 1300

Patent

active

061579904

ABSTRACT:
A multi-port RAM (MPRAM) having a SRAM and a DRAM on a single chip. Separate pins are provided on the chip to supply independent chip select signals for the SRAM and the DRAM. When the SRAM chip select signal is at a high level, a clock generator is prevented from producing an internal clock signal for the SRAM. As a result, no SRAM operation is performed in response to a SRAM command. Similarly, when the DRAM chip select signal is high, a clock generator produces no internal clock signal for the DRAM. As a result, DRAM operations are prevented from being performed in response to DRAM commands.

REFERENCES:
patent: 5561781 (1996-10-01), Braceras et al.
patent: 5566318 (1996-10-01), Joseph
patent: 5734621 (1998-03-01), Ito

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