Patent
1996-05-23
1999-05-25
Lee, Thomas C.
395892, G06F 1300
Patent
active
059076844
ABSTRACT:
A computer system and processing method are provided for coupling multiple physical processing nodes together, wherein each physical processing node is characterized as having its own memory, by either at least one channel which is independent of and coupled to the multiple physical processing nodes or by at least one input/output (I/O) processor, again which is independent of and coupled to the multiple physical processing nodes. The at least one channel and/or the at least one I/O processor couple the multiple physical processing nodes to at least one shared input/output device. Sharing of the at least one channel and/or at least one I/O processor is practical by providing "indirect logical addressing" using logical address tables within the channel subsystem. The logical address tables associate an image identifier (Image.sub.-- ID) and processing node identifier (PN.sub.-- ID) concatenation with an indexed logical address for use in communicating I/O operation parameters across the at least one channel.
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Halma Marten Jan
Sachs Martin William
Augspurger Lynn L.
Cutter Lawrence D.
International Business Machines - Corporation
Lee Thomas C.
Ton David
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