Independent array grounds for flash EEPROM array with paged eras

Details Independent array grounds for flash EEPROM array with paged eras Independent array grounds for flash EEPROM array with paged eras

1993-08-23

1994-11-15

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Erase

365185, 365900, G11C 1300

Patent

active

053654846

ABSTRACT:
An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generating a half-sector ground line signal. The separate individual ground line is connected to the ground line circuit for receiving the half-sector ground line signal which is at a predetermined positive potential during erase.

REFERENCES:
patent: 5077691 (1991-02-01), Haddad et al.
patent: 5282170 (1994-01-01), Van Buskirk et al.

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