Incrementer based on carry chain compression

Details Incrementer based on carry chain compression Incrementer based on carry chain compression

2009-06-08

2010-02-02

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

07656190

ABSTRACT:
A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive-OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output.

REFERENCES:
patent: 7538579 (2009-05-01), Schleicher et al.
patent: 7555741 (2009-06-01), Milton et al.
patent: 7565388 (2009-07-01), Baeckler et al.

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