Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-01-11
2001-11-20
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S016000
Reexamination Certificate
active
06321363
ABSTRACT:
FIELD OF INVENTION
Invention relates to computer-aided verification tools, particularly incremental simulation of electronic circuit designs.
BACKGROUND OF INVENTION
In electronic circuit design, engineers use may conventional logic simulator for design verification, such that when design problem is discovered during simulation, for example, engineers may seek to identify and correct certain circuit component or portion of subject design that causes such problem. Then, after design correction, revised design is often re-simulated. Depending design size and complexity, simulation time may vary significantly. Further, during chip-level or system integration phase, circuit design changes usually require re-simulation of entire chip or system, resulting in increased simulation time, which may detrimentally impact product delivery.
SUMMARY OF INVENTION
Invention resides in automated electronic design methodology and system for reducing re-simulation time, whereby previous simulation results and knowledge of changes made to design are used.
Accordingly, given simulation model V, for example, whereby prior simulation approach took X amount of time to run simulator to come up with simulation result R, then improvement is provided over prior approach, such that V becomes V′, wherein improved re-simulation scheme operates using V, V′, and R values, and new simulation result R′ is thereby obtained in substantially shorter time than X, through effective usage of previous simulation result R and knowledge about difference between V and V′.
Furthermore, when integrated with hardware description language (HDL) debugger, such incremental or re-simulation scheme substantially improves engineer productivity, particularly at chip or system integration level design verification. Accordingly, different design versions and corresponding simulation results are more easily stored and managed.
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Huang Yen-Son
Lee Chia-Huei
Lu Martin
Tsai Jensen
Kik Phallaka
Novas Software Inc.
Smith Matthew
Smith-Hill and Bedell
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