Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-29
2010-10-12
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07814451
ABSTRACT:
Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in accordance with Newtonian mechanics are approximated by numerical integration. A resultant time-evolving system of nodes moves through a continuous location space in continuous time, and is used to derive placements of the morphable-devices having one-to-one correspondences with the nodes. Nodes under the influence of net attractive forces, computed based on the interconnections between the morphable devices, tend to coalesce into well-organized topologies. Nodes are also affected by spreading forces determined by density fields that are developed based on local spatial node populations.
REFERENCES:
patent: 5568636 (1996-10-01), Koford
patent: 5625575 (1997-04-01), Goyal
patent: 5754444 (1998-05-01), Koford
patent: 5818726 (1998-10-01), Lee
patent: 5838583 (1998-11-01), Varadarajan et al.
patent: 5875117 (1999-02-01), Jones
patent: 6085032 (2000-07-01), Scepanovic
patent: 6088519 (2000-07-01), Koford
patent: 6282693 (2001-08-01), Naylor et al.
patent: 6301693 (2001-10-01), Naylor et al.
patent: 6360356 (2002-03-01), Eng
patent: 6557153 (2003-04-01), Dahl
patent: 6591407 (2003-07-01), Kaufman et al.
patent: 6662348 (2003-12-01), Naylor et al.
patent: 6665851 (2003-12-01), Donelly et al.
patent: 6671859 (2003-12-01), Naylor et al.
patent: 6725438 (2004-04-01), van Ginneken
patent: 6757878 (2004-06-01), Srinivasan et al.
patent: 6766500 (2004-07-01), Donelly et al.
patent: 6782520 (2004-08-01), Igusa et al.
patent: 6901567 (2005-05-01), Irie
patent: 6910199 (2005-06-01), Sachs
patent: 6957407 (2005-10-01), Suto
patent: 7065729 (2006-06-01), Chapman
patent: 7103863 (2006-09-01), Riepe et al.
patent: 7178118 (2007-02-01), Ramachandran et al.
patent: 2002/0138816 (2002-09-01), Sarrafzadeh et al.
patent: 2002/0198695 (2002-12-01), Sherman
patent: 2003/0046050 (2003-03-01), Padilla
patent: 2003/0187626 (2003-10-01), Catto
patent: 2004/0078770 (2004-04-01), Miller et al.
patent: 2004/0123262 (2004-06-01), Shirota et al.
patent: 2004/0617250 (2004-07-01), Boucher
patent: 2004/0181380 (2004-09-01), Yoshida
patent: 2004/0225971 (2004-11-01), Donelly et al.
patent: 2004/0225982 (2004-11-01), Donelly et al.
patent: 2004/0230931 (2004-11-01), Barbee et al.
patent: 2005/0086040 (2005-04-01), Davis
patent: 2005/0125758 (2005-06-01), Lembach et al.
patent: 2005/0278667 (2005-12-01), Boucher et al.
patent: 2007/0150846 (2007-06-01), Furnish
patent: 2007/0204252 (2007-08-01), Furnish
patent: 1907957 (2007-01-01), None
patent: 1020010087374 (2003-07-01), None
patent: 1020040032109 (2005-11-01), None
patent: 1020010033623 (2009-06-01), None
patent: 2004061725 (2004-07-01), None
patent: WO 2007/002799 (2007-01-01), None
patent: 2007146966 (2007-12-01), None
patent: 2007147084 (2007-12-01), None
patent: 2007147150 (2007-12-01), None
patent: 2007149717 (2007-12-01), None
patent: 2008005622 (2008-01-01), None
Ren et al.,“Sensitivity Guided Net Weighting for Placement Driven Synthesis”, 2004, ACM, Technical Paper (8 pages).
Hockney, R.W. and Eastwood, J.W., Computer Simulation Using Particles, Adam Hilger, 1989, pp. 1-43, 94-165.
Hockney, R.W. and Eastwood, J.W., Computer Simulation Using Particles, Adam Hilger, 1989, pp. 166-265.
Hockney, R.W. and Eastwood, J.W., Computer Simulation Using Particles, Adam Hilger, 1989, pp. 266-352.
Birdsall, Charles K. and Langdon, A. Bruce, Plasma Physics Via Computer Simulation, McGraw-Hill Book Company, 1985, pp. 1-79.
Birdsall, Charles K. and Langdon, A. Bruce, Plasma Physics Via Computer Simulation, McGraw-Hill Book Company, 1985, pp. 155-253.
U.S. Appl. No. 11/953,048, filed Dec. 8, 2007, Dozier et al.
U.S. Appl. No. 11/967,186, filed Dec. 29, 2007, Lebrun.
U.S. Appl. No. 11/967,187, filed Dec. 29, 2007, Furnish.
U.S. Appl. No. 11/967,182, filed Dec. 29, 2007, Furnish.
U.S. Appl. No. 11/967,180, filed Dec. 29, 2007, LeBrun.
U.S. Appl. No. 11/967,183, filed Dec. 29, 2007, LeBrun.
U.S. Appl. No. 11/967,184, filed Dec. 29, 2007, Bose.
U.S. Appl. No. 11/967,185, filed Dec. 29, 2007, Furnish.
U.S. Appl. No. 11/967,179, filed Dec. 29, 2007, Furnish.
U.S. Appl. No. 12/301,456, filed Nov. 18, 2008, Bose.
U.S. Appl. No. 11/427,333, filed Jun. 28, 2006, Furnish.
U.S. Appl. No. 11/953,048, filed Dec. 8, 2007, Dozier.
U.S. Appl. No. 60/869,250, filed Dec. 8, 2006, Blomgren.
U.S. Appl. No. 60/804,690, filed Jun. 14, 2006, Furnish.
Non-final Office Action dated Aug. 20, 2008 for U.S. Appl. No. 11/684,522.
Response filed Jan. 21, 2009 to non-final OA dated Aug. 20, 2008 for U.S. Appl. No. 11/684,522.
Final OA dated Apr. 28, 2009 for U.S. Appl. No. 11/684,522.
Non-final OA dated Nov. 18, 2008 for U.S. Appl. No. 11/744,758.
Response filed Feb. 18, 2009 in response to non-final OA dated Nov. 18, 2008 for U.S. Appl. No. 11/744,758.
Final Office Action dated Jun. 11, 2009 for U.S. Appl. No. 11/744,758.
Alupoaei, Net-Based Force-Directed Macrocell Placement for Wirelength Optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, No. 6, Dec. 2002.
Search Report for WO2007002799 dated Dec. 1, 2006.
Naveed A. Sherwani, Algorithms for VLSI Physical Design Automation, Third Edition, Springer, Nov. 30, 1998, pp. 219-246.
Michael John Sebastian Smith, Application-Specific Integrated Circuits, Pearson Education, Inc., 1997, pp. 873-893.
Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, pp. 185-216.
Bose Subhasis
Furnish Geoffrey Mark
LeBrun Maurice J.
Lin Sun J
Schwabe Williamson & Wyatt P.C.
LandOfFree
Incremental relative slack timing force model does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Incremental relative slack timing force model, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Incremental relative slack timing force model will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4181621