Incremental lithography mask layout design and verification

Details Incremental lithography mask layout design and verification Incremental lithography mask layout design and verification

2005-06-07

2005-06-07

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C430S005000

Reexamination Certificate

active

06904587

ABSTRACT:
A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.

REFERENCES:
patent: 6493865 (2002-12-01), Fischer et al.
patent: 6553558 (2003-04-01), Palmer et al.
patent: 6578190 (2003-06-01), Ferguson et al.
patent: 6609245 (2003-08-01), Liebmann et al.
patent: 2002/0166108 (2002-11-01), Rittman

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