Incremental checkpointing in a multi-threaded architecture

Details Incremental checkpointing in a multi-threaded architecture Incremental checkpointing in a multi-threaded architecture

2007-07-10

2007-07-10

Beausoliel, Robert (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S010000, C714S011000

Reexamination Certificate

active

10651376

ABSTRACT:
A processor executes corresponding instruction threads as a leading thread and a trailing thread. For a selected instruction, processor state corresponding to the execution of the instruction is saved in a history buffer. This is performed before writing a result from the selected instruction to a destination register. The result from executing the selected instruction in the leading thread is compared to the result from executing the selected instruction in the trailing thread. If the comparison indicates a fault, then restoring the processor state corresponding to a previous instruction. Data from the history buffer is used to perform the restoration.

REFERENCES:
patent: 5938775 (1999-08-01), Damani et al.
patent: 6023772 (2000-02-01), Fleming
patent: 6058491 (2000-05-01), Bossen et al.
patent: 6317821 (2001-11-01), Batten et al.
patent: 6326809 (2001-12-01), Gambles et al.
patent: 6519730 (2003-02-01), Ando et al.
patent: 6598122 (2003-07-01), Mukherjee et al.
patent: 2001/0034854 (2001-10-01), Mukherjee
Haitham Akkary, Michael A. Driscoll, “A Dynamic Multithreading Processor,” Proceedings of the 31st Annual International Symposium on Microarchitecture, Nov. 30-Dec. 2, 1998, pp. 1-11, Dallas, Texas, USA.
Seon Wook Kim, Et Al., “Reference Idempotency Analysis: A Framework for Optimizing Speculative Execution,” Proceedings of the SIGPLAN Symposium on Principals and Practice of Parallel Programming (PPoPP), Jun. 18-20, 2001, pp. 1-10, Snowbird, Utah, USA.
Deborah T. Marr, Et Al., “Hyper-Threading Technology Architecture and Microarchitecture,” Intel Technology Journal QI, 2002, pp. 1-12.
Shubhendu S. Mukherjee, Et Al., “Detailed Design and Evaluation of Redundant Multithreading Alternatives,” 29th Annual International Symposium on Computer Architecture (ISCA), 2002, pp. 1-12.
Steven K. Reinhardt, Shubhendu S. Mukherjee, “Transient Fault Detection via Simultaneous Multithreading,” 27th Annual International Symposium on Computer Architecture, Jun. 2000, pp. 1-12.

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