Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-01-31
2000-04-18
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, 711148, G06F 1200
Patent
active
060527617
ABSTRACT:
The system and method for performing an update operation on the sharing list in a multi-node SCI-based system involves issuing an update command from a first node in the list to the remaining nodes in the sharing list, however the first node maintains its position at a head position in the sharing list. The first node issues an increment command to each successive node in the list until the end of the list is reached. Each node receives the increment command and updates its cache and then sends a reply back to the first node, listing the state of the node and a pointer to the next node. The method and system also prevents a node from rolling out of the sharing list before that node receives the update command. Each node has a phase value that is toggled as the node is incremented. Thus, a rollout request will be nullified unless the phase value of the rollout request matches the phase value of the node. The system and method also interlocks the rollout requests to inhibit a node that is being rolled out from being incremented.
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Hornung Bryan
Marietta Bryan
Bataille Pierre-Michel
Cabeca John W.
Hewlett--Packard Company
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