Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1999-10-29
2002-10-22
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S029000
Reexamination Certificate
active
06470402
ABSTRACT:
The invention relates to a procedure for the transfer of data from N channels, which are sampled in a pre-determined sequence, to a processor by means of a circular FIFO store with n storage stages, whilst retaining this pre-determined sequence, whereby the output of the last stage is connected to the input of the first stage.
It is known that a circular FIFO memory, also known as a FIFO ring store, may be used as an intermediate storage device for the transfer of data. An example of such a FIFO ring store is described in the publication “Halbleiterschaltungstechnik” (Semiconductor circuit technology) by U. Tietze and Ch. Schenk, 9th edition, page 286. The write and read processes are controlled by a write pointer (input pointer) and a read pointer (output pointer), respectively, which in each case indicate into which storage stage data may be written and from which storage stage data may be read. Once this FIFO store is full, no further data must be input, as otherwise data may be overwritten which have not yet been read. Situations may be imagined where an overwriting process is harmless, but the known ring store does not make provision for measures which would permit such innocuous overwriting. Since no overwriting of any store contents is allowed, not much flexibility exists when considered in conjunction with a processor with which the data will have to be further processed. In the case of the known FIFO ring store no measures are taken which will ensure that a processor will always read from a block from a pre-determined number of consecutive storage stages, as there is no guarantee that the block contains current data and that the reading process starts in the first stage of the block and that it ends with the last stage of the block.
Reading a block of connected data values is already being used in a type MAX
125
or MAX
126
data acquisition circuit from Messrs. MAXIM. This circuit provides four input channels by means of which an input signal can be sampled. The sampling values are stored in an intermediate store which comprises four stages, and which collects the sampling values in their successive sampling order. The four sampling values now form a block which may subsequently be read by a processor. Since only four sampling values can be stored, the processor must execute a read process whenever the store is full. This means that the processor is time-restricted as regards its processing cycle, as it may well be desirable to execute read operations at longer intervals, that is intervals which are greater than the time difference between two successive signal sampling operations at the four input channels. Even with this known data transfer process, the processor is limited in its flexibility with respect to the read operations of the data required by it.
The invention rests on the requirement to provide a procedure for the transfer of data, the use of which will enhance the flexibility with respect to the temporal control of reading processes by a processor without loss of data integrity.
This requirement is met by a procedure for the transfer of data sampled from N channels in a pre-determined sequence, to a processor by means of a circular FIFO store with n storage stages, whilst retaining this pre-determined sequence, whereby the output of the last stage is connected to the input of the first stage, by implementing the following steps:
a) With each write operation of data into the FIFO store, a write pointer is set to a value which designates the storage stage into which has been written last;
b) with each reading operation of data from the FIFO store, a read pointer is set to a value which designates the storage stage which is subsequently to be read, whereby the reading process always comprises the reading of data from i×N storage stages, i being an integer and i×N<n;
c) a trigger pointer is set to a value j×N, j being an integer, j×N<n and i<j;
d) if, after a write process, the value of the write pointer is equal to or greater than the value of the trigger pointer, a read operation is allowed;
e) after each read operation the value of the trigger pointer is increased by one trigger step of i×N, and
f) when the value of the write pointer reaches the value of the read pointer, the value of the read pointer and the value of the trigger pointer will be increased by N.
By the use of the procedure according to the invention, once a read process has been allowed, a processor can read and further process one or more data blocks contained in successive stages of a store. Even if any data stored are overwritten by newly arrived data, on account of the circular structure of the FIFO storage device and because of the relatively large temporal separation between two read operations, the use of the trigger pointer and the forward stepping of the read pointer ensure that, for the next read operation, the processor will always start at the storage stage containing the first data value of a data block, and in this way guarantee the continued coherence between the signals derived from the channels sampled and the signals read by the processor. Considerable flexibility on the part of the processor is therefore ensured with respect to the temporal control of the read operations.
Advantageous further developments of the invention are indicated in the sub-claims.
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patent: 4700391 (1987-10-01), Leslie et al.
patent: 5347637 (1994-09-01), Halford
patent: 5696940 (1997-12-01), Liu et al.
patent: 5706203 (1998-01-01), Kawauchi
patent: 5974483 (1999-10-01), Ray et al.
patent: 0 391 584 (1990-03-01), None
Beckemeyer Heinz-Peter
Christ Manfred
Oed Richard
Brady W. James
Gaffin Jeffrey
Kempler William B.
Park Ilwoo
Telecky , Jr. Frederick J.
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