Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-05-13
2004-11-16
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S374000, C257S389000, C257S395000, C257S396000, C257S397000, C257S401000, C257S410000
Reexamination Certificate
active
06818950
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
Not applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
REFERENCE TO AN APPENDIX
Not applicable.
BACKGROUND
1. Technical Field
This disclosure relates generally to integrated circuits (“IC,” also referred to hereinafter as “chip(s)”) and more particularly to arrayed, or cellular, metal-oxide-semiconductor (MOS) transistors, also commonly known in the art as MOSFETs (metal-oxide-semiconductor field-effect transistor(s)).
2. Description of Related Art
FIG. 1
(Prior Art) schematically illustrates an elevation view taken in a cross-section through a small region of a conventional, multi-element, n-channel, lateral MOSFET array integrated circuit. MOS and complementary metal oxide silicon (“CMOS”) device fabrication technology is a preferred process for many integrated circuit devices, particularly those in which low power consumption and high component density are priorities. Many publications describe the details of common techniques used in chip fabrication that can be generally employed in the manufacture of complex, three-dimensional, IC structures, including the present invention; see e.g., “Silicon Processes,” Vol. 1-3, copyright 1995, Lattice Press, Lattice Semiconductor Corporation, Hillsboro, Oreg., or “VLSI Technology,” McGraw-Hill, 1988. Moreover, the individual steps of such processes can be performed using commercially available IC fabrication machines. The use of such machines and conventional fabrication step techniques will be referred to hereinafter as simply: “in a known manner.” As specifically helpful to an understanding of the present invention, approximate technical data are disclosed herein based upon current technology; future developments in this art may call for appropriate adjustments as would be apparent to one skilled in the art. Therefore no further explanation, other than that specifically provided herein, is necessary for an understanding for those persons skilled in the art. It should also be recognized by those skilled in the art that the specific embodiment descriptions herein are exemplary of the art and the invention and that instead of conductivity types described, complimentary types can be employed in each case, changing the polarity of the device, e.g., respectively exchanging p-type ion (e.g., boron) doping for n-type ion (e.g., phosphorus) doping. No limitation on the scope of the invention is intended by the inventors by use of these exemplary embodiments and none should be implied therefrom.
Using for example 1.2 micron fabrication technology rules, each MOSFET of an array structure
100
, is constructed on a doped (approximately 5-20 ohm-cm) p-type substrate
101
(approximately 500 micron thick). Generally there is formed a buried isolation (ISO) layer
103
(approximately 10-15 micron thick; doping factor of approximately 1E
18
/cm
2
) separating the substrate
101
from a superjacent epitaxial layer (approximately 7-10 microns thick) of the structure
100
, where a P-type buried layer is used for isolation or parasitic NPN transistor suppression, a N-type buried layer is uses for parasitic PNP bipolar transistor suppression. Superjacent the buried ISO layer
103
is a lightly doped, P−, well
105
(approximately 3-4 microns thick; doping factor of approximately 2E
18
/cm
3
) in which the active elements of the IC are formed. Each conventional MOSFET arrayed in the epitaxial layer includes a source (“S”) and drain (“D”) with an intervening channel region. A heavily doped, − type ion, poly-silicon gate (“G”; thickness approximately 5,000 Angstroms; doping factor of approximately 10
21
/cm
3
) above the channel for turning the MOSFET on and off, each with appropriate electrical interconnects (often simply referred to as “metal
1
,” “metal
2
,” et seq. as appropriate to the particular implementation). A conventional gate oxide
113
(approximately 500 Angstrom thickness) intermediates the gates and the channel regions between source and drain regions of each MOSFET.
The elevation view depiction here is through a plane representative of a minute region of an IC, showing two adjacent MOSFET parts of a cellular array wherein the cross-section is in a plane through two adjacent, heavily doped (approximately 1E
20
/cm
3
), N+, source or drain (“S/D”) regions
107
,
107
a
(approximately 0.35 micron thick). Source/drain electrical interconnect contacts
111
,
111
a
, are provided, generally a metal deposited through vias in an upper chemical-vapor-deposition (CVD) oxide
115
layer (approximately one micron thick).
In such an IC array, it is known to form a large plurality (e.g, tens of thousands per square inch surface area) of MOSFETs. Particular design sets of such structures and processes for fabrication are described in U.S. Pat. No. 5,355,008 for a DIAMOND SHAPED GATE MESH FOR CELLULAR MOS TRANSISTOR ARRAYS, and U.S. Pat. No. 5,447,876, for a METHOD OF MAKING A DIAMOND SHAPED GATE MESH FOR CELLULAR MOS TRANSISTOR ARRAYS, assigned to the common assignee herein and incorporated by reference in their entireties. Said gate mesh forms a structure having a plurality of substantially identical openings, each of said opening approximating a predetermined geometric construction. In general, these structures have been found to be particularly suited to closed-cell power MOSFET arrays, constructed to achieve low specific resistance in that the poly-silicon gate structures are arranged as overlaying and interspersing the source regions and drain regions by forming geometric grid, or mesh, like gate structures in accordance with the predetermined chosen shape. It is convenient to describe the array by the shape of the poly-silicon gate structures
109
, e.g., “diamond cellular structure,” “hexagonal cellular structure,” “propeller cellular structure,” or the like—see also e.g.,
FIG. 2
, described in detail hereinafter. Such gate structures are therefore referred to hereinafter as “geometric gate constructions” (GGC).
However, it has been found that the geometric gate constructions may result in increased gate to source and drain capacitance—that is, an increased inherent capacitance between the poly-silicon gate fingers forming the mesh and the epitaxial layer, P− well, of the silicon. Such an additional gate to source and drain capacitance. lowers the switching speed of the device.
BRIEF SUMMARY
The basic aspects of the invention generally provide for processes and structures which increase switching speed of geometric gate construction MOSFETS.
As an exemplary embodiment, there is described a cellular metal-oxide-semiconductor structure having a plurality of individual field effect transistors, the structure including: a poly-silicon gate construction having a predetermined geometric mesh configuration; and subjacent each intersection of said mesh, a substantially insulative material plug inter-spaced between adjacent source regions and adjacent drain regions of said structure.
As another exemplary embodiment, there is described a MOSFET array including: a semiconductor material having a top surface; a plurality of lateral metal-oxide-semiconductor transistors in a cellular array configuration with respect to said top surface, each of said transistors including a first region of a geometric gate construction overlying and insulated from the top surface proximate a transistor channel region between a transistor source region and transistor drain region in said top surface, said gate construction forming a mesh having a plurality of substantially identical openings, each of said opening approximating a predetermined geometric shape; and subjacent each intersection of said mesh, each intersection forming a second region of the geometric gate construction overlying and insulated from the top surface proximate a third region of said top surface intervening adjacent source regions and adjacent drain regions of said transistors, an inherent capacitance-reducing plug.
As another exemplary embodiment, there is described a method for increasing switch
Micrel Inc.
Tortolano J. Vincent
Tran Minhloan
Tran Tan
Valet Eugene H.
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