Increased propagation speed across integrated circuits

Details Increased propagation speed across integrated circuits Increased propagation speed across integrated circuits

2000-08-31

2001-08-07

Wong, Don (Department: 2821)

Communications: radio wave antennas

Antennas

Microstrip

Reexamination Certificate

active

06271795

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to methods and circuit configurations for increasing the propagation speed of a signal across an integrated circuit and/or for eliminating clock distribution networks from integrated circuits.
BACKGROUND INFORMATION
FIG. 1
(Prior Art) is a simplified top-down diagram illustrative of a field programmable gate array (FPGA) integrated circuit
1
. Integrated circuit
1
includes a ring of bond pads
2
, an inner core of configurable logic blocks
3
, and a fork-shaped clock distribution network
4
. A clock signal present on a clock input pad
5
passes through a clock buffer
6
, is distributed vertically through a vertical clock bus
7
, passes through clock buffers
8
-
12
, and then propagates horizontally from left to right through corresponding horizontally extending clock buses
13
-
17
. In the bottom most clock bus
17
, the clock signal propagates left to right from clock buffer
12
, past point
18
, and down the clock bus to point
19
.
FIG. 2
(Prior Art) is a simplified cross-sectional diagram of a portion of integrated circuit
1
showing a section of clock bus
17
. Numerous layers of Metallization
20
and dielectric material
21
are disposed over the substrate
22
of the integrated circuit
1
. In the illustrated example, the metal of the clock bus
17
is insulated from other layers of metal above it and below it by dielectric material
21
.
FIG. 3
(Prior Art) illustrates a series of RC trees
23
that is often used to model the propagation of a clock signal down such a clock bus. Points
18
and
19
in
FIG. 3
correspond to points
18
and
19
in
FIG. 1
, respectively. The larger the resistance R, the longer it will take for the clock signal to propagate from point
18
to point
19
. Similarly, the larger the capacitance C, the longer it will take for the clock signal to propagate from point
18
to point
19
. Resistance R represents the distributed resistance of the clock bus being modeled. The capacitance C represents the distributed capacitance of the clock bus. The larger the dielectric constant K of the dielectric material separating the clock bus
17
from the other conductors of
FIG. 2
, the larger the distributed capacitance C.
In the example of
FIG. 1
, the propagation delay of the clock signal across the integrated circuit chip means that an edge of the clock signal will arrive at point
19
after it has arrived at point
18
. This difference in time when the clock edge arrives is called “clock skew”. In a digital integrated circuit, it is often desired to keep the magnitude of the clock skew within a certain percentage of the period of the clock signal. For example, it may be desired to keep the clock skew within ten percent of the clock period. A given clock edge is to arrive at all logic blocks within the same time period (ten percent of the clock period). A clock signal having a frequency of 500 megahertz has a period of two nanoseconds. Accordingly, in this example, if the clock signal is to arrive at all logic blocks within ten percent of the clock period, then the clock signal must be able to propagate across the integrated circuit in about two tenths of a nanosecond. Integrated circuits today can be 2.5 centimeters on a side and the locations where clock signals are required can easily be two centimeters apart. For the clock signal to travel two centimeters in two tenths of a nanosecond requires a propagation speed of about 10
8
meters per second. Achieving such a high propagation speed across an integrated circuit is difficult.
Moreover, future advances in semiconductor processing technology are likely to lead to a desire to increase clock speeds into the gigahertz range. Such an increase in clock speed would further reduce the amount of time available for a clock signal to travel across an integrated circuit. Moreover, future integrated circuits may be even larger than integrated circuits of today. Such increases in size will likely result in the clock signal having to travel even greater distances. It is therefore foreseen that clock speeds of future integrated circuits may be limited by the propagation speed of clock signals on the integrated circuits.
SUMMARY
The propagation velocity of an electromagnetic wave through a transmission medium is limited by the inductance and capacitance per unit length of the medium. In the
V
=
1
K
⁢
Vac
(
equ
.
 
⁢
1
)
context of a clock signal traveling down a clock bus surrounded by an interlayer dielectric in a conventional integrated circuit, this means that the maximum propagation speed V of the clock signal is limited by the dielectric constant K of the dielectric to be a fraction of the speed of light in a free space Vac in accordance with equation 1 below. The larger the dielectric constant K, the slower the clock signal will travel. Silicon dioxide, a common dielectric used for interlayer dielectric in conventional integrated circuits, has a dielectric constant of roughly four. The maximum velocity for a clock signal traveling laterally across an integrated circuit down a clock bus that is surrounded by silicon dioxide is therefore approximately 1.5×10
8
meters per second (about one half the speed of light in free space).
It is recognized, however, that the velocity of an electromagnetic wave travelling through air is quite close to the speed of light in free space. The dielectric constant of dry air is almost exactly one. The present invention in one embodiment takes advantage of this fact.
In accordance with one embodiment of the present invention, a clock signal is transmitted as an electromagnetic wave that propagates in air in a direction substantially parallel to the upper surface of an integrated circuit. Due to the wave propagating in air, its velocity is very close to that of the speed of light in free space (3×10
8
meters per second). At a location on the integrated circuit where the clock signal is to be used, an antenna and receiving circuit are provided. The antenna is connected to the input of the receiving circuit. The electromagnetic wave propagates through the air across the upper surface of the integrated circuit at a high velocity. When it reaches the antenna it induces a corresponding signal in the antenna. This signal is then amplified by the receiving circuit to output the clock signal. One or more pairs of such antennas and receiving circuits are disposed across the surface of the integrated circuit, one at each location where the clock signal is needed. Skew between the various clock signals output by the various receiving circuits is reduced due to the increased propagation velocity of the electromagnetic wave over the upper surface of the integrated circuit.
In accordance with some embodiments, a field programmable gate array has no clock distribution network of clock buses. Rather than conducting a clock signal around the integrated circuit on a distribution network of metal conductors, the clock signal is transmitted as an electromagnetic wave to antennas that are distributed across the integrated circuit at locations where the clock signal is to be used. Elimination of the clock distribution network frees up routing resources for other uses. In some embodiments, some of the sequential logic of a field programmable gate array is coupled to a clock distribution network whereas other operating sequential logic of the field programmable gate array is not connected to the clock distribution network but rather is clocked by a clock signal that is received on a local antenna.
Other structures and methods are disclosed in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.


REFERENCES:
patent: 5019829 (1991-05-01), Heckman et al.
patent: 5023624 (1991-06-01), Heckaman et al.
patent: 5142698 (1992-08-01), Koga et al.
patent: 5629838 (1997-05-01), Knight et al.
patent: 5969559 (1999-10-01), Schwartz

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