Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch
Reexamination Certificate
2000-06-15
2002-10-29
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
With lattice constant mismatch
C257S018000
Reexamination Certificate
active
06472695
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to semiconductor devices, and in particular to increased lateral oxidation rates of aluminum indium arsenide (AlInAs).
2. Description of the Related Art
Silicon semiconductor devices have dominated the electronics field for many years. The reason that silicon is widely favored as a base substrate material for semiconductors is the ability to produce semiconducting material, i.e., silicon, and an insulating material i.e., silicon oxide, with good electrical and mechanical properties. The presence of both semiconducting material and insulating material is important for isolation, refractive indices, and other desired electrical and optical properties. However, silicon devices have limitations in speed and in the infrared spectrum. As such, the focus for new materials to be used in these high speed and optical domains has shifted to gallium arsenide (GaAs), indium phosphide (InP), other III-V compounds, and alloys thereof.
Although GaAs does not have a natural oxide like silicon does, techniques have been developed to provide a lattice-matched oxide for GaAs devices through the wet thermal oxidation of aluminum gallium arsenide (AlGaAs). However, a suitable material for oxidation to be used in conjunction with InP devices has been unavailable. Attempts have been made to use aluminum arsenide antimonide (AlAsSb) as a wet oxidation material, and even though AlAsSb is lattice matched to InP, wet oxidation of AlAsSb leaves an elemental layer of antimony at the oxide-semiconductor interface, which is unacceptable from both electrical and optical standpoints.
Other attempts at finding a lattice-matched material for InP devices have focused on aluminum indium arsenide (AlInAs). Related art attempts to thermally wet oxidize AlInAs have shown that the low aluminum mole fraction of lattice-matched AlInAs slows the rate of oxidation, and requires higher temperatures to perform the oxidation, which degrades the surface quality of the AlInAs. The degradation of the surface quality makes the AlInAs related art attempts unacceptable for use in the optical regime, and makes the resultant devices more difficult to process and produce in the electrical regime.
It can be seen, then, that there is a need in the art for a material that can be used as an oxide in conjunction with InP. It can also be seen that there is a need in the art for an InP quasi-lattice-matched material that can be thermally wet oxidized without excessive temperature. It can also be seen that there is a need in the art for an InP-based material that can be thermally wet oxidized at a higher oxidation rate.
SUMMARY OF THE INVENTION
To minimize the limitations in the prior art described above, and to minimize other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a device and a method for producing an oxidizable digital alloy that is nearly strain-compensated, such that it can be deposited without substantial defects on indium phosphide. The device comprises a layer of semiconductor material, a first layer, and a second layer. The first layer is indium arsenide and is coupled to the layer of semiconductor material, wherein the first layer of indium arsenide is under a compressive strain by a lattice mismatch between the layer of semiconductor material and the first layer of indium arsenide. The second layer is aluminum arsenide and is coupled to the layer of indium arsenide, wherein the second layer of aluminum arsenide is under a tensile strain by a lattice mismatch between the second layer and the first layer. The first layer and the second layer comprise a digital alloy of aluminum indium arsenide, and create a material that is approximately strain-compensated on the layer of semiconductor material therein. A superlattice period of the first layer of indium arsenide and a second layer of aluminum arsenide is selected to allow an oxide of desired depth to be produced from the digital alloy.
An object of the invention is to provide a material that can be used as an oxide in conjunction with InP. Another object of the invention is to provide an InP quasi-lattice-matched material that can be thermally wet oxidized without excessive temperature. Another object of the invention is to provide an InP based material that can be thermally wet oxidized at a higher oxidation rate.
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Coldren Larry A.
Hall Eric M.
Gates & Cooper LLP
The Regents of the University of California
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