Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-04-28
2001-06-26
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S321000, C257S322000, C257S324000, C257S325000
Reexamination Certificate
active
06252270
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a semiconductor device and, more specifically, to a semiconductor device having a flash EEPROM structure containing a substantial concentration of deuterium therein.
BACKGROUND OF THE INVENTION
The use of silicon in semiconductor devices, such as Floating-Gate Avalanche-injection MOS transistors (“FAMOS”) and Floating-Gate tunnel-oxide transistor (“FLOTOX”) is well known. Equally well known is the time dependent degradation of these devices, which is often referred to as the hot carrier degradation effect. Typically, the FAMOS and FLOTOX structures have to withstand many program and erase operations, which is usually at least 10
4
cycles. After so many program and erase operations, the threshold voltage window (i.e., the difference after program and erase) decreases due to the deterioration of the oxide quality in terms of interface traps, injection efficiency, and leakage.
It is believed that the interface traps are caused by defects that are generated by current flow in such semiconductor devices, and it is further believed that these defect states reduce the mobility and lifetime of the carriers and cause degradation of the device's performance. In most cases, the substrate comprises silicon, and the defects are thought to be caused by dangling bonds (i.e., unsaturated silicon bonds) that introduce states in the energy gap, which remove charge carriers or add unwanted charge carriers in the device, depending in part on the applied bias. While dangling bonds occur primarily at surfaces or interfaces in the device, they also are thought to occur at vacancies, micropores and dislocations, and are also thought to be associated with impurities. To alleviate the problems caused by such dangling bonds, a hydrogen passivation process has been adopted and has become a well-known and established practice in the fabrication of such devices.
In the hydrogen passivation process, it is thought that the defects that affect the operation of semiconductor devices are removed when the hydrogen bonds with the silicon at the dangling bond sites. While the hydrogen passivation process eliminates the immediate problem associated with these dangling bonds, it does not eliminate degradation permanently because the hydrogen atoms that are added by the passivation process can be “desorbed” or removed from the previous dangling bond sites by the “hot carrier effect.”
A hot carrier is an electron or hole that has a high kinetic energy, which is imparted to it when voltages are applied to electrodes of the device. Under such operating conditions, the hydrogen atoms, which were added by the hydrogen passivation process, are knocked off by the hot electrons. This hydrogen desorption results in aging or degradation of the device's performance. According to established theory, this aging process occurs as the result of hot carriers stimulating the desorption of hydrogen from the silicon substrate's surface or the silicon dioxide interface. This hot carrier effect is particularly of concern with respect to smaller devices in which proportionally larger electric fields can be used.
Accordingly, what is needed in the art is a semiconductor device and a method of manufacture therefore that does experience the level of efficiency degradation experienced by the devices that are passivated with conventional hydrogen passivation processes. The present invention addresses these needs.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a programmable semiconductor device and a method of manufacturing the same. The device includes: (1) a substrate, which in one embodiment contains at least in part silicon, (2) a dielectric layer located over the substrate and (3) a control gate located over the dielectric layer. The dielectric layer contains a substantial concentration of an isotope of hydrogen. In one embodiment of the present invention, the substrate contains at least one doped region. Those who are skilled in the art will understand that the present invention is employable to form semiconductor devices having one or more doped regions therein.
The present invention therefore introduces the broad concept of employing, in lieu of hydrogen, an isotope of hydrogen to passivate a dielectric layer in a programmable semiconductor device. For purposes of the present invention, “substantial concentration” is defined as a concentration of at least about 10
16
cm
−3
of a hydrogen isotope.
In one embodiment of the present invention, the isotope is deuterium. However, the principles of the present invention may be applied to heavier isotopes of hydrogen.
In one embodiment of the present invention, the semiconductor device further comprises a floating gate proximate the control gate. The semiconductor device is selected from the group consisting of: (1) a floating-gate avalanche-injection metal oxide semiconductor transistor (“FAMOS”) and (2) a floating-gate tunnel-oxide semiconductor transistor (“FLOTOX”). In one aspect of this particular embodiment, the floating gate includes a substantial concentration of the hydrogen isotope as defined above, and in another aspect, the floating gate is deuterated polysilicon. The present invention can, of course, be applied to other known or later-discovered programmable semiconductor devices.
In one embodiment of the present invention, the control gate contains a substantial concentration of a hydrogen isotope. In one aspect of this particular embodiment, the control gate is deuterated polysilicon.
In one embodiment of the present invention, the hydrogen isotope decreases interface traps between the dielectric layer and the control gate. In addition, when present, the hydrogen isotope also decreases interface traps between the substrate and the dielectric layer and between the polysilicon, control gate and the floating gate. These interface traps grow over time, eventually rendering the device harder to program. However, it is believed that the presence of the hydrogen isotope in the dielectric layer decreases the interface traps, thereby extending the number of cycles that the device can be programmed and erased.
In one embodiment of the present invention, the dielectric layer is formed from a gas selected from the group consisting of deuterated steam, deuterated tetraethylorthosilane (TEOS) or deuterated silane (SiD
4
).
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those who are skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention are described below and form the subject of the claims of the invention. Those who are skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those who are skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 3903325 (1975-09-01), Horiuchi
patent: 4268321 (1981-05-01), Meguro
patent: 4268951 (1981-05-01), Elliott et al.
patent: 4620211 (1986-10-01), Baliga et al.
patent: 4851370 (1989-07-01), Doklan et al.
patent: 5248348 (1993-09-01), Myachi et al.
patent: 5304830 (1994-04-01), Sato
patent: 5352636 (1994-10-01), Beinglass
patent: 5378541 (1995-01-01), Ihara et al.
patent: 5595927 (1997-01-01), Chen et al.
patent: 5642014 (1997-06-01), Hillenius
patent: 5646050 (1997-07-01), Li et al.
patent: 5744202 (1998-04-01), Nickel
patent: 5776831 (1998-07-01), Padmanabhan et al.
patent: 5830575 (1998-11-01), Warren et al.
patent: 5872387 (1999-02-01), Lyding et al.
patent: 5990008 (1999-11-01), Koyama et al.
patent: 61-264350 (1986-11-01), None
patent: 64-41211 (1989-02-01), None
patent: 1-211970 (1989-08-01), None
patent: 2-277269 (1990-11-01), None
patent: 2-2772
Gregor Richard W.
Kizilyalli Isik C.
Singh Ranbir
Agere Systems Guardian Corp.
Crane Sara
Tran Thien F.
LandOfFree
Increased cycle specification for floating-gate and method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Increased cycle specification for floating-gate and method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Increased cycle specification for floating-gate and method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2487888