Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2011-08-30
2011-08-30
Smith, Matthew (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S025000, C257SE21400, C257SE29168, C438S285000
Reexamination Certificate
active
08008649
ABSTRACT:
A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.
REFERENCES:
patent: 4721983 (1988-01-01), Frazier
patent: 4959696 (1990-09-01), Frensley et al.
patent: 5552330 (1996-09-01), Tehrani et al.
patent: 6218677 (2001-04-01), Broekaert
patent: 7002175 (2006-02-01), Singh et al.
patent: 7465953 (2008-12-01), Koh et al.
patent: 2004/0209416 (2004-10-01), Holonyak et al.
patent: 2008/0073641 (2008-03-01), Cheng et al.
patent: 2009/0127542 (2009-05-01), Sugaya et al.
Seong Jin Koh Strategies for Controlled Placement of Nanoscale Building Blocks, Nanoscale Research Letters vol. 2, No. 11, pp. 519-545 Published online: Oct. 9, 2007.
Woodward, et al., “Integration of a Resonant-Tunneling Structure with a Metal-Semiconductor Field-Effect Transistor,” Appl. Phys. Lett. 51, 1542-1544 (1987).
Chou, et al., “Observation of Electron Resonant Tunneling in a Lateral Dual-Gate Resonant Tunneling Field-Effect Transistor,” Appl. Phys. Lett. 55, 176-178 (1989).
Ismail, et al., “Lateral Resonant Tunneling in a Double-Barrier Field Effect Transistor,” Appl. Phys. Lett., 55, 589-591 (1989).
Ismail, et al., “A Planar Resonant Tunneling Field Effect Transistor,” IEEE Trans. Elec. Devices 36, 2617 (1989).
Yang, et al., “Analysis of the Performance of the Quantum Wire Resonant Tunneling Field-Effect Transistor,” Superlattices and Microstructures vol. 27, 245-254 (2000).
Yen, et al., “Monolithic Integrated Resonant Tunneling Diode and Heterostructure Junction Field Effect Transistor Circuits,” Solid-State Electronics vol. 39, 1449-1455 (1996).
Register, et al., “Resonant-Injection-Augmented Field-Effect Transistor for Low-Voltage Switching” at the 4thInternational Nanotechnology Conference, Tokyo, Japan, Apr. 14-17, 2008.
Banerjee Sanjay
Register, II Leonard Franklin
Board of Regents , The University of Texas System
Smith Matthew
Swanson Walter H
Voigt, Jr. Robert A.
Winstead P.C.
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