Inclusion vector architecture for a level two cache

Details Inclusion vector architecture for a level two cache Inclusion vector architecture for a level two cache

1997-06-20

1999-11-30

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711119, 711125, 711126, 711144, G06F 1208

Patent

active

059960485

ABSTRACT:
A cache architecture with a first level cache and a second level cache, with the second level cache lines including an inclusion vector which indicates which portion of that line are stored in the first level cache. In addition, an instruction/data bit in the inclusion vector indicates whether a portion of that line is in the instruction cache at all. Thus, when a snoop is done to the level two cache, additional snoops to the level one cache only need to be done for those lines which are indicated as present by the inclusion vector.

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