Inclusion map for accelerated cache flush

Details Inclusion map for accelerated cache flush Inclusion map for accelerated cache flush

1997-11-03

2001-03-20

Yoo, Do Hyun (Department: 2759)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S133000, C711S143000, C711S135000, C711S005000

Reexamination Certificate

active

06205521

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to data processing systems and in particular to a cache map that accelerates cache memory operations.
BACKGROUND OF THE INVENTION
Cache memories are small, relatively high speed memories used in most modern data processing systems to temporarily replicate portions of main memory which are currently in use by a central processing unit (CPU). By segmenting memory into higher speed cache and lower speed main memory, a substantial increase in software execution rate can be experienced since most programs access the same portions of memory over and over again. Therefore, by keeping as much of the actively needed data as possible in the cache, the CPU avoids the need to access the slower main memory.
Cache memories operate by mirroring the contents of main memory in a way which is typically transparent to the CPU. For example, each memory address generated by the CPU is first passed to a cache controller. The cache controller keeps track of which portions of main memory are currently assigned to the cache. On each memory access, if the cache is currently assigned to hold the contents of the requested address, a “cache hit” occurs and the cache is enabled to complete the access, whether it be a write access or a read access. If this is not the case, a “cache miss” has occurred, and the main memory is enabled for access. When a miss occurs, the cache typically assigns the requested miss address to itself, fetches the data from memory, and if necessary, displaces the contents of a corresponding cache location.
Also common in data processing systems such as personal computers are power management features whereby the CPU may be shut down during periods of non-use in order to conserve energy. In order for such features to avoid corrupting data in the main memory, power management activities must be coordinated with so-called “cache flushing.” Cache flushing is an operation by which the contents of the cache are copied back to main memory, and must typically be performed prior to a power down sequence in order to avoid losing data. It is therefore common to include a so-called “dirty” bit with each cache location, indicating whether the data for the cache location is different from the corresponding data in the main memory. Thus, during the flushing operation, the system walks through the list of dirty bits for each cache location to determine whether the data must be written back to main memory prior to continuing with the power management sequence.
While the need to check each cache location for coherency with respect to the main memory was not a particular problem when cache memories were of a fairly small size, it is now common for cache memories to include many megabytes. Therefore, the time for a cache flushing operation is no longer insignificant; indeed, it is quite possible that the cache flushing operation itself may consume a significant portion of the total power dissipation of the system. As a result, the system may consume significantly more power than otherwise necessary during idle periods. The user may also end up having to wait for the system to complete a cache flushing operation, which tends to minimize any visible benefit from enabling power management features in the first place, especially when the processor is only lightly loaded.
SUMMARY OF THE INVENTION
In brief summary, a cache memory in accordance with the present invention is arranged in blocks, with each block containing a number of cache line locations. The system also contains a cache flush map having an inclusion map that includes a bit for each cache block. The inclusion bits act as a summary of the state of individual cache dirty bits for the cache lines in the associated block; that is, the inclusion bit is set if one or more of the dirty bits are set for those cache lines.
Whenever data is written to any of the cache lines in a given block, the inclusion bit associated with that block is set. The inclusion bit is cleared when the associated block is written back to main memory, when the associated block is otherwise written back to main memory, or when the main memory and cache otherwise become coherent.
As a result, the state of the inclusion bit map always indicates which blocks within the cache might contain new data. Therefore, when it becomes time to flush the cache, only those blocks whose corresponding inclusion bit is set need to be checked.
The invention is also a process for flushing a cache as part of a power management process in which a block inclusion bit is set according to the states of cache line valid bits associated with each of several cache lines in a cache block. During a cache flushing operation executed as part of a power management cycle, the state of each inclusion bit is read. If the inclusion bit is set, then the cache lines in the associated block are checked to see whether they need to be written back to main memory. If, however, the associated block inclusion bit is not set, then no flushing of the associated block is necessary.
The invention therefore provides substantial benefits especially where only small portions of a cache memory are changed between successive power management operations.


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