Static information storage and retrieval – Read/write circuit – Testing
Patent
1986-05-13
1989-11-07
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Testing
364716, 371 222, 365185, H03K 1977, G06F 1126
Patent
active
048796883
ABSTRACT:
An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.
REFERENCES:
patent: 4041459 (1977-08-01), Horninger
patent: 4399523 (1983-08-01), Gerber et al.
patent: 4441074 (1984-04-01), Bockett-Pugh et al.
patent: 4490812 (1984-12-01), Guterman
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4625311 (1986-11-01), Fitzpatrick et al.
patent: 4761768 (1988-08-01), Turner et al.
"A High-Speed ESFI SOS Programmable Logic Array with an MNOS Version", IEEE J. Solid-State Cir., vol. SC-10, No. 5, Oct. 1975, pp. 331-335, by K. Horninger.
Press Release by Lattice Semiconductor Corporation dated Apr. 23, 1985.
Data Sheet for 53D1641/63D1641, Monolithic Memories, Inc., Bipolar LSI Databook, Fifth Edition, 1983, pp. 3-37 to 3-35.
"Shadow Register Architecture Simplifies Digital Diagnostics", J. Birner et al., Systems Design Handbook, Monolothic Memories, Inc., 1983, pp. 2-4 to 2-15.
Duane H. Oto et al., "High Voltage Regulation and Process Considerations for High Density 5V-Only E.sup.2 PROM'S", IEEE Journal of Solid State Circuits, vol. SC-18, No. 5, Oct. 1983.
Steve Landry, "Application-Specific ICs Relying RAM Implement Almost Any Logic Function," Electronic Design, Oct. 31, 1985, pp. 123-130.
John F. Dickson, "On Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique", IEEE Journal of Solid State Circuits, vol. SC-11, No. 3, Jun. 1975, pp. 374-378.
Carver Mead and Lynn Conway, "Introduction to VLSI Systems," 1980, pp. 82-84.
Darling Roy D.
Rutledge David L.
Turner John E.
Lattice Semiconductor Corporation
Popek Joseph A.
LandOfFree
In-system programmable logic device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with In-system programmable logic device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and In-system programmable logic device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-87309