In-situ SOG etchback and deposition for IMD process

Details In-situ SOG etchback and deposition for IMD process In-situ SOG etchback and deposition for IMD process

1996-04-01

1998-12-15

Chang, Ceila

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438706, 438707, 438710, 438711, 438712, 438715, 216 63, 216 67, 216 70, 216 97, H01L 21306

Patent

active

058496408

ABSTRACT:
A method is disclosed for improved planarization and deposition of intermetal dielectric layers in semiconductor substrates. More specifically, the method involves the performance of specific process steps in-situ. That is, unlike in prior art, starting with cured spin-on-glass (SOG), the steps of SOG etchback and deposition of the intermetal dielectric PECVD, all take place sequentially in the same chamber and without a vacuum break. If not in the same chamber, then in the same load lock system. In this manner, it is shown that no longer does the SOG layer delaminate from the oxide layer. Furthermore, because the system is not exposed to moisture due to the absence of vacuum break, there is no adverse reaction when metal is deposited into the via holes. It is also shown that the behavior of SOG can be further improved when it is subjected to, after etchback, to argon sputter treatment, and/or oxygen plasma treatment in-situ, that is, without a vacuum break from the time the SOG etchback is performed to the time of depositing the next layer of PECVD oxide over the planarized surface. As a by-product of the steps enumerated above, the disclosed method also reduces the contact resistance of metal interfaces in via holes.

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