Optics: measuring and testing – Dimension
Reexamination Certificate
2000-02-10
2004-04-06
Font, Frank G. (Department: 2877)
Optics: measuring and testing
Dimension
C356S630000
Reexamination Certificate
active
06717685
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The following invention relates generally to micro electronics manufacturing, and specifically to proximity X-ray lithography.
2. Related Art
Large scale integrated circuits (LSIs) are continuing to push the envelope of increasing a complexity on sermiconductor chips, with the advent of very large scale integrated circuits (VLSIs) and ultra large scale integrated circuits (ULSIs). An increasing number of circuit elements, like transistors, resistors, and capacitors are added with metal interconnections, to increase the size and complexity of chips.
Semiconductor chips are manufactured using a series of masks in the lithographic process. During lithography, successive patterns of materials on and regions in a semiconductor wafer are chemically or photochemically induced onto the surface of the wafer using the mask as a template. The patterns, including lines and holes, define the circuit elements, such as transistors.
Initially, the semiconductor wafer is covered with resist material, such as photoresist. The resist material is responsive to incident energy, such as an electromagnetic radiation. Examples of electromagnetic waves used are visible light, ultraviolet light, electron beams, and x-rays. Where the resist material is exposed to the radiation, it chemically activates the resist, by for example etching a hole in the substrate.
In lithography, the mask is used to determine where the electromagnetic radiation is permitted to contact the resist material. The mask functions to mask certain regions of the resist material from the incident energy but not other regions, by permitting the radiation to pass through some regions (called transmissive regions), and preventing the radiation from passing through other regions (called non-transmissive regions).
There are different types of lithography. One type of lithography uses projection optics. In this type of lithography, the pattern on the mask is reduced in size using special optical lenses before being transmitted to the resist material using the incident energy.
Another type of lithography is proximate lithography. In this type of lithography, there is a one-to-one correspondence in size between the pattern and the mask, meaning the pattern is not reduced or enlarged in size before being transmitted onto the mask using the incident energy. In proximate lithography, the size of the printing gap (also called an exposure gap or space) between the resist on the wafer and the mask is quite significant. For modem chips, gaps on the order of 10-40 microns are required for the patterns.
Proximate lithography exposure and aligner tools are machines used to align the mask on the wafer. There are numerous aligners used by persons skilled in the art. One manufacturer of an aligner is Silicon Valley Group Lithography (SVGL). Another manufacturer is Suss Advanced Lithography (SAL).
For modern chips, pattern lines having dimensions on the order of less than 200 nanometers must be drawn. The smaller the width of the pattern line, the narrower the exposure gap that is required. For a 200 nm dimension, gap sizes on the order of 20 micrometers are required.
The gap can vary because of such factors as: illumination non-uniformities, which are non-uniformities based on varying illuminations by the incident energy source (i.e., different exposures in different areas on the wafer); the wafer being originally placed such that the gap is non-uniform; and non-uniformities caused by the movement of the wafer, either when it is brought in the proximity to the mask during exposure or moved along the plane of the wafer during the exposure (known as stepping).
Typically, the gap is not measured directly when incident energy exposures are performed. The gap is measured between exposure steps of the aligner and exposure tool, when the tool exposes the mask to incident energy. It is hoped that the gap does not change during the exposure step. The average gap between the mask and the wafer, as well as the tilt (or the variation in the gap between different regions of the wafer) is not known during actual exposure.
This exposure gap verification is difficult to perform directly, because time consuming scanning electron microscopy measurements are needed to infer the exposure gap. Therefore, independent verification of the gap settings of the, exposure and aligner tool cannot be performed frequently, because of the time consuming, difficult procedures involved. What is required is a simpler, less time-consuming, more cost-effective way of determining the exposure gap between the exposure steps of the exposure tool.
SUMMARY OF THE INVENTION
The present invention is directed to a method, and a system for implementing the method, for determining an exposure gap between a mask and a resist material, where the resist material is exposed to an incident energy transmitted through exposure regions of the mask. The method includes the steps of: providing first gratings on one or more sides of a first structure defined by one or more first regions of the mask; providing second gratings on one or more sides of a second structure defined by one or more second regions of the mask; exposing the first and the second structures to the incident energy; measuring a difference between a location in the first structure and a location in the second structure; and extrapolating the exposure gap from the difference.
In one embodiment, a mask writing tool is used to provide the first gratings and the second gratings.
The step of providing the first gratings can include the step of: providing gratings on a pair of adjacent edges of an internal box structure defined by the one or more first regions. The step of providing the second gratings includes the step of: providing gratings on a pair of adjacent edges of an external box structure defined by the one or more second regions located opposite from the pair of adjacent edges of the internal box structure.
In one embodiment, the step of providing the first gratings includes the step of: providing gratings on a pair of opposite edges of an internal box structure defined by the one or more first regions. In this embodiment, the step of providing the second gratings includes the step of: providing gratings on a first edge of the internal box structure and on a second edge of an external box structure defined by one of the second regions, the first and the second edge being located opposite from one another.
In another embodiment, the step of providing the first gratings includes the step of: drawing a plurality of pattern lines having relatively thin width portions and relatively thicker finger projectile portions on a semiconductor resist material, the thin width portions and the finger projectile portions placed in an adjacent manner to form a comb-like pattern. The step of providing the second gratings can also include the step of: drawing a plurality of pattern lines having relatively thin width portions and relatively thicker finger projectile portions on a semiconductor resist material, the thin width portions and the finger projectile portions placed in an adjacent manner to form a comb-like pattern.
In one embodiment, the method further includes providing the first gratings and the second gratings to have the same pattern line widths. In another embodiment, the method further includes providing the first gratings and the second gratings to have different pattern line widths from one another.
The above measuring step can include the step of: measuring a difference between a center in the first box structure and a center in the second box structure. The above extrapolating step can include the step of: applying an empirical relationship between a given pattern line width, a given exposure gap, and a given line shortening effect to determine the exposure gap. A proximate lithography metrology tool can be used to implement the applying step.
REFERENCES:
patent: 5285259 (1994-02-01), Saitoh
patent: 5327221 (1994-07-01), Saitoh et al.
patent: 5373232 (1994-12-01), Cresswell et al.
BAE Systems Information
Font Frank G.
Merlino Amanda
Swidler Berlin Shereff & Friedman, LLP
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