Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2011-05-31
2011-05-31
Ghyka, Alexander G (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S219000, C438S295000, C438S597000, C438S788000, C257SE21545, C257SE21546, C257SE21550, C257SE21553, C257SE21585
Reexamination Certificate
active
07951683
ABSTRACT:
In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots is provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. Prior to etch back, the feature gap is plugged with an etch selectivity layer. The etch back part of the process involves multiple steps including a sputter etch to reduce the top hat formations followed by a reactive plasma etch to open the gap. This method improves gapfill, reduces the use of high cost fluorine-based etching and produces interim gaps with better sidewall profiles and aspect ratios.
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Chang Leonard
Ghyka Alexander G
Novellus Systems, Inc
Weaver Austin Villeneuve & Sampson LLP
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