In situ preclean in a PVD chamber with a biased substrate config

Details In situ preclean in a PVD chamber with a biased substrate config In situ preclean in a PVD chamber with a biased substrate config

1996-01-22

1998-09-15

Nguyen, Nam

Chemistry: electrical and wave energy

Processes and products

Coating, forming or etching by sputtering

20419213, 20429806, 20429811, 2041923, C23C 1434

Patent

active

058074678

ABSTRACT:
Disclosed is PVD deposition chamber which is modified with an electrical circuit that allows a voltage bias to be applied to any one or more of a target, an in-process integrated circuit wafer, and collimator. The collimator can also be isolated from the electrical circuit. This configuration allows a preclean of the in-process integrated circuit wafer in situ in the PVD deposition chamber by ion sputtering and a subsequent sputter deposition through the collimator.
A method is also disclosed wherein an in-process integrated circuit wafer is first precleaned in the PVD deposition chamber by applying a negative voltage bias to the in-process integrated circuit wafer. A film of conducting material is then sputter deposited on the surface of the in-process integrated circuit wafer by applying a negative voltage bias to the target. The collimator is electrically isolated during this process or is set at a higher potential than the in-process integrated circuit wafer. A voltage bias can also be applied to the in-process integrated circuit wafer during the deposition, and its magnitude proportioned to modify the morphology of the film being deposited. Once the deposition is conducted, a negative voltage bias can be applied to the collimator to sputter clean the collimator.

REFERENCES:
patent: 4243865 (1981-01-01), Saxena
patent: 4585517 (1986-04-01), Stemple
patent: 4717462 (1988-01-01), Homma et al.
patent: 4816126 (1989-03-01), Kamoshida et al.
patent: 4913789 (1990-04-01), Aung
patent: 4999096 (1991-03-01), Nihei et al.
patent: 5089441 (1992-02-01), Moslehi
patent: 5108570 (1992-04-01), Wang
patent: 5171402 (1992-12-01), Talieh et al.
patent: 5330628 (1994-07-01), Demaray et al.
patent: 5391394 (1995-02-01), Hansen
patent: 5403459 (1995-04-01), Guo
patent: 5409587 (1995-04-01), Sandhu
IBM Technical Disclosure Bulletin, "A Method . . . ULSI Applications", vol. 37, No. 06A, Jun. 1994, pp. 463-464.
Wolf, Multilevel-Interconnect Technology for VLSI and ULSI, "Silicon Processing in the VLSI Era," vol. 2, p. 219, 1986.
C. Nender, S. Berg, B. Gelin, and B. Stridh, "Selective Deposition of Ti: An Interface Study," Institute of Technology, Uppsala University, Uppsala, Sweden, Sci. Technol., A, vol. 5, No. 4, Jul./Aug. 1987.

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