Semiconductor device manufacturing: process – Including control responsive to sensed condition
Reexamination Certificate
2001-12-13
2003-12-02
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
C438S007000, C438S010000, C438S011000, C438S016000, C438S018000, C438S522000, C438S530000, C438S540000
Reexamination Certificate
active
06656749
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacturing of semiconductor devices, and more particularly, to laser anneal processes that minimize overmelt of source/drain regions.
BACKGROUND OF THE INVENTION
Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor(MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS semiconductor device includes a semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS transistor is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
MOS devices typically fall in one of two groups depending on the type of dopants used to form the source, drain and channel regions. The two groups are often referred to as n-channel and p-channel devices. The type of channel is identified based on the conductivity type of the channel which is developed under the transverse electric field. In an n-channel MOS (NMOS) device, for example, the conductivity of the channel under a transverse electric field is of the conductivity type associated with n-type impurities (e.g., arsenic or phosphorous). Conversely, the channel of a p-channel MOS (PMOS) device under the transverse electric field is associated with p-type impurities (e.g., boron).
A type of device, commonly referred to as a MOS field-effect-transistor (MOSFET), includes a channel region formed in the semiconductor substrate beneath the gate area or electrode and between the source and drain regions. The channel is typically lightly doped with a dopant having a conductivity type opposite to that of the source/drain regions. The gate electrode is generally separated from the substrate by an insulating layer, typically an oxide layer such as SiO
2
. The insulating layer is provided to prevent current from flowing between the gate electrode and the source, drain or channel regions. In operation, a voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner an electric field is used to control the current flow through the channel region.
The semiconductor industry is continually striving to improve the performance of MOSFET devices. The ability to create devices with sub-micron features has allowed significant performance increases, for example, from decreasing performance degrading resistances and parasitic capacitances. The attainment of sub-micron features has been accomplished via advances in several semiconductor fabrication disciplines. For example, the development of more sophisticated exposure cameras in photolithography, as well as the use of more sensitive photoresist materials, have allowed sub-micron features, in photoresist layers, to be routinely achieved. Additionally, the development of more advanced dry etching tools and processes have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials used in MOSFET structures.
As the distance between the source region and the drain region of the MOSFET (i.e., the physical channel length) decreases, in the effort to increase circuit speed and complexity, the junction depth of source/drain regions must also be reduced to prevent unwanted source/drain-to-substrate junction capacitance. However, obtaining these smaller junction depths tests the capabilities of current processing techniques, such as ion implantation with activation annealing using rapid thermal annealing. Rapid thermal annealing typically involves heating the silicon wafer, after implanting, under high-intensity heat lamps. Implanting or doping usually amorphizes the silicon substrate, and the activation annealing is used to recrystallize the amorphized silicon region.
As a result of the limitations of rapid thermal annealing, laser thermal annealing is being implemented, particularly for ultra-shallow junction depths. Laser thermal annealing may be performed after ion implantation of a dopant and involves heating the doped area with a laser. The laser radiation rapidly heats the exposed silicon such that the silicon begins to melt. The diffusivity of dopants into molten silicon is about eight orders of magnitude higher than in solid silicon. Thus, the dopants distribute almost uniformly in the molten silicon and the diffusion stops almost exactly at the liquid/solid interface. The heating of the silicon is followed by a rapid quench to solidify the silicon, and this process allows for non-equilibrium dopant activation in which the concentration of dopants within the silicon is above the solid solubility limit of silicon. Advantageously, this process allows for ultra-shallow source/drain regions that have an electrical resistance about one-tenth the resistance obtainable by conventional rapid thermal annealing.
A problem associated with forming source/drain regions using laser thermal annealing is controlling the energy. Although amorphous silicon absorbs energy at a higher rate than crystalline silicon, and therefore, the fluence of the laser can adjusted to melt only to a depth that the silicon has been amorphized, the fluence must be initially set. If the setting is too low, the dopant does not fully activate in the source/drain regions, and if the setting for fluence is too high, overmelt into the substrate can occur. Furthermore, process conditions may change over time and cause the required fluence of the laser to also change. Accordingly, a need exists for an improved laser anneal process that allows for real-time adjustment of the fluence of the laser to provide a more precise control of the melting depth and to reduce the incidence of overmelting.
SUMMARY OF THE INVENTION
This and other needs are met by embodiments of the present invention which provide a method of manufacturing a semiconductor device. The method includes thermal annealing source/drain regions with a laser, measuring a depth of the source/drain regions, and adjusting at least one parameter of the laser used in the thermal annealing process. After the laser is adjusted, the source/drain regions are laser thermal annealed again, and the process is repeated until a desired depth of the source/drain regions is obtained.
By measuring the depth of the source/drain regions immediately after laser thermal annealing and adjusting the laser thermal anneal process, a lower initial fluence can be used during the laser thermal annealing process. In so doing, the likelihood of overmelt of the source/drain regions into the substrate can be reduced. Also, the depth of the source/drain regions can be more finely controlled.
In a further aspect of the present invention, the parameters to be adjusted
Ogle Robert B.
Paton Eric N.
Tabery Cyrus E.
Xiang Qi
Yu Bin
Advanced Micro Devices , Inc.
Fourson George
Maldonado Julio J.
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