In-situ etch of multiple layers during formation of local...

Details In-situ etch of multiple layers during formation of local... In-situ etch of multiple layers during formation of local...

1997-09-05

2001-10-02

Gulakowski, Randy (Department: 1746)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C216S049000, C216S072000, C438S725000, C438S740000

Reexamination Certificate

active

06297167

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods for providing local interconnections between two or more regions within a semiconductor device.
BACKGROUND ART
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. To take advantage of increasing number of devices and to form them into one or more circuits, the various devices need to be interconnected.
To accomplish interconnection on such a small scale, a local interconnect is typically used within an integrated circuit to provide an electrical connection between two or more conducting or semi-conducting regions (e.g., active regions of one or more devices). For example, a plurality of transistors can be connected to form an inverting logical circuit using a local interconnect.
The local interconnect is typically a low-resistance material, such as a conductor or doped semiconductor, that is formed to electrically couple the selected regions. For example, in certain arrangements, damascene techniques are used to provide local interconnects made of tungsten (W), or a like conductor, which is deposited within an etched opening, such as via or trench that connects the selected regions together. The use of lower-level local interconnects reduces the coupling burden on the subsequently formed higher layers to provide such connectivity, which reduces the overall circuit size and as such tends to increase the circuit's performance. Accordingly, there is a continuing need for more efficient and effective processes for forming local interconnects.
SUMMARY OF THE INVENTION
The present invention provides an in-situ etching process for creating local interconnects using damascene techniques that provides better process control, reduces processing failures, speeds production, and reduces manufacturing costs. The in-situ etching process includes forming openings in a semiconductor wafer having a plurality of layers by using an etching tool to first etch through selected portions of a first underlying layer of the semiconductor wafer using a mixture of C
4
F
8
/CH
3
F gasses. The selected portions of the first underlying layer are defined by etch windows formed by a mask layer formed on the first underlying layer.
The method further includes using the same etching tool to etch away the mask layer using O
2
gas. In certain embodiments, the first underlying layer is a dielectric layer, such as, for example, an oxide layer. The method in other embodiments also includes supplying Argon (Ar) gas to the etching tool when etching either of the first underlying and mask layers.
In yet other embodiments, the method includes using the same etching tool to further etch through selected portions of a second underlying layer, that is below the first underlying layer, using a mixture of CH
3
F/O
2
gasses. In these embodiments, the selected portions of the second underlying layer are defined by etched openings in the first underlying layer that correspond to the etch windows in the mask layer. In certain embodiments of the present invention, the second underlying layer is a stop layer, such as, for example, a silicon nitride (e.g., Si
3
N
4
), or silicone oxynitride (e.g., SiO
x
N
y
, referred to hereinafter simply as SiON) layer.
In still other embodiments, the method also includes depositing a conductive material within a local interconnect opening that was etched in-situ and extends through the first and second underlying layers. In certain embodiments, the conductive layer includes tungsten (W).
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


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