In situ doped embedded sige extension and source/drain for...

Details In situ doped embedded sige extension and source/drain for... In situ doped embedded sige extension and source/drain for...

2007-02-13

2007-02-13

Le, Thao X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

C257S063000, C257S347000

Reexamination Certificate

active

10905598

ABSTRACT:
Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.

REFERENCES:
patent: 6621131 (2003-09-01), Murthy et al.
patent: 6893919 (2005-05-01), Chuang et al.
patent: 6906360 (2005-06-01), Chen et al.
patent: 6991972 (2006-01-01), Lochtefeld et al.
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patent: 2005/0093076 (2005-05-01), Steegen et al.
patent: 2006/0057859 (2006-03-01), Chen

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