Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove
Reexamination Certificate
2002-06-10
2003-09-16
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Groove
C257S626000
Reexamination Certificate
active
06621147
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of semiconductor manufacture, and more particularly to a method for reducing surface tension and warpage on a semiconductor wafer during semiconductor device manufacture and an inventive structure resulting therefrom.
BACKGROUND OF THE INVENTION
During the manufacture of semiconductor devices such as dynamic random access memories (DRAMs), static random access memories (SRAMs), microprocessors, logic, etc., several semiconductor wafer assembly structures are commonly formed. For example, a semiconductor wafer is doped then dielectric layers, polysilicon layers, and metal features such as contact plugs and bond pads are formed over the wafer.
FIG. 1
depicts a planar semiconductor wafer assembly
10
having a plurality of unsegmented semiconductor dice
12
formed thereon.
Other layers commonly formed after formation of the bond pads include coating layers
14
such as a plasma-deposited passivation layer. The passivation layer often comprises more than one layer. For example, a first tetraethyl orthosilicate (TEOS) layer between about 2,150 angstroms (Å) and about 2,450 Å can be formed over the wafer surface, then a sputter etch can be performed to reduce breadloafing and keyholing between metal lines. This results in a first TEOS layer between about 500 Å and about 600 Å. Subsequently, a second TEOS layer is deposited to a thickness of between about 10,850 Å and about 11,150 Å, then a silicon nitride layer at a thickness of between about 3,680 Å and about 4,320 Å. The passivation layer functions as an alpha barrier and/or a passivation layer to reduce damage to the semiconductor device from mechanical contact or chemical contaminants.
After forming the passivation layer, a protective polyimide layer can be formed to function as a die coat which protects the passivation layers from cracking, for example from contact with a lead frame in a “leads-over-chip” assembly. The polyimide material can comprise an organic material spun onto the wafer surface. A polyimide which is sensitive to ultraviolet light can be used or, in the alternative, a UV-sensitive resist is patterned over the polyimide to expose the bond pads. The polyimide (or the resist) is exposed to a patterned UV source, and the polyimide is etched from the bond pads and any other necessary locations such as fuse banks. A negative resist/polyimide can also be used. After etching the polyimide from the bond pads and other areas, a final cure of the polyimide is performed, for example by exposing the polyimide to a temperature of from about 200° C. to about 350° C. for a period of about 9 hours. This step drives out solvents from the polyimide and reduces the layer thickness from about 14 microns to about 9 microns and leaves a hardened film.
Another process used with semiconductor devices includes the removal of a portion of the backside of the semiconductor wafer to produce a thinner semiconductor device, in a process referred to as “backgrinding” or “backlapping.” This process includes protecting the front (circuit side) of the wafer with an adhesive tape or a spun-on photoresist, then backgrinding or polishing the back of the wafer until the desired wafer thickness is achieved. A typical process thins the wafer from a starting thickness of 30 mils (0.79 millimeter) to as thin as 7 or 8 mils (0.18 millimeter to 0.20 millimeter), for example to form thin small outline package (TSOP) devices.
An obvious result of thinning the wafer is that it becomes more fragile and susceptible to damage. With less resistance to flexing, additional care in processing and transporting the wafer must be taken to minimize scrap. In addition to flexing, a wafer can warp which is known to result in various manufacturing problems such as misaligned and poorly focused photolithography which can affect, for example, patterning of the polyimide to expose the bond pads and fuse banks.
FIG. 2
depicts a wafer assembly
20
exhibiting a degree of warping.
Warped wafers have also been found to contribute to wafer breakage. For example, transporting the wafers can be performed using a flexible chuck which holds the wafer through the application of a vacuum. It is difficult to maintain an airtight seal between an excessively warped wafer and the flexible chuck, and thus the wafer can dislodge from the chuck and become damaged from contact with external surfaces. A method and structure which results in less warpage to the wafer and less damage and scrap would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method and resulting structure which reduces problems associated with the manufacture of semiconductor devices, particularly problems resulting from warped wafers.
In accordance with one embodiment of the invention a semiconductor wafer assembly comprising a semiconductor wafer and a plurality of unsegmented semiconductor dice is provided. A coating such as a passivation layer or polyimide layer as previously described, or another coating layer, is formed over the front (circuit side) of a semiconductor wafer.
After forming the coating layer a series of grooves is chemically or mechanically etched in the coating layer. The wafer itself can remain unetched, or a small groove only partially through the wafer can be etched therein. The grooves have been found to reduce the severity of wafer warping and to decrease various problems associated with warped wafers as described below. After etching the grooves through the coating layer various additional wafer processing steps can be performed, such as backgrinding the wafer. Finally, the wafer is diced and device processing continues, for example die attach, wire bond, and encapsulation steps.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
REFERENCES:
patent: 3677875 (1972-07-01), Althouse
patent: 4096619 (1978-06-01), Cook, Jr.
patent: 4722130 (1988-02-01), Kimura et al.
patent: 5016080 (1991-05-01), Giannella
patent: 5071792 (1991-12-01), VanVonno et al.
patent: 5185292 (1993-02-01), VanVonno et al.
patent: 5414297 (1995-05-01), Morita et al.
patent: 5476566 (1995-12-01), Cavasin
patent: 5480842 (1996-01-01), Clifton et al.
patent: 5824595 (1998-10-01), Igel et al.
patent: 5888883 (1999-03-01), Sasaki et al.
patent: 5943591 (1999-08-01), Vokoun et al.
patent: 6075280 (2000-06-01), Yung et al.
patent: 6107164 (2000-08-01), Ohuchi
patent: 6162703 (2000-12-01), Muntifering et al.
patent: 6184109 (2001-02-01), Sasaki et al.
patent: 2001/0001502 (2001-05-01), Wong
patent: 2002/0000642 (2002-01-01), Lin et al.
patent: 2002/0014682 (2002-02-01), Sakai et al.
patent: 2002/0043700 (2002-04-01), Sasaki et al.
The Chip Packaging Manual, An Introduction to Semiconductor Assembly Operations and Companion Study Guide to “Chip Packaging” Video Training Program, by Peter Van Zant and Donald Mason, 1987.
Toshiba Develops Paper-Thin Package, by Yoshiko Hara, EE Times, Jun. 2, 1999.
Jr. Carl Whitehead
Martin Kevin D.
Micro)n Technology, Inc.
Smoot Stephen W.
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