In package ESD protections of IC using a thin film polymer

Details In package ESD protections of IC using a thin film polymer In package ESD protections of IC using a thin film polymer

2011-01-18

2011-01-18

Fureman, Jared J (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000

Reexamination Certificate

active

07872841

ABSTRACT:
A packaged semiconductor device (200) with a substrate (220) having, sandwiched in an insulator (221), a flat sheet-like sieve member (240) made of a non-linear material switching from insulator to conductor mode at a preset voltage. Both member surfaces are free of indentations; the member is perforated by through-holes, which are grouped into a first set (241) and a second set (242). Metal traces (251) over one member surface are positioned across the first set through-holes (241); each trace is connected to a terminal on the substrate top and, through the hole, to a terminal on the substrate bottom. Analogous for metal traces (252) over the opposite member surface and second set through-holes (242). Traces (252) overlap with a portion of traces (252) to form the locations for the conductivity switches, creating local ultra-low resistance bypasses to ground for discharging overstress events.

REFERENCES:
patent: 5444593 (1995-08-01), Allina
patent: 7279724 (2007-10-01), Collins et al.
patent: 7528467 (2009-05-01), Lee
patent: 2007/0127175 (2007-06-01), Shrier
patent: 2009/0257166 (2009-10-01), Kim et al.

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