In-memory, in-page directory cache coherency scheme

Details In-memory, in-page directory cache coherency scheme In-memory, in-page directory cache coherency scheme

2011-08-02

2011-08-02

Bradley, Matthew (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S141000, C711S159000

Reexamination Certificate

active

07991963

ABSTRACT:
In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing coherency information associated with the demanded cache line from a memory unit by bringing in from a memory page in which the demanded cache line is stored, the memory page also including a directory line having coherency information corresponding to the demanded cache line; reading data associated with the demanded cache line in accordance with the coherency information; and returning the data to the processor.

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Office Action Received for German Patent Application No. 102008062 044.0, mailed on Feb. 25, 2010, 4 Pages of Office Action and 4 Pages of English Translation.

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