In-line voltage contrast detection of PFET silicide...

Details In-line voltage contrast detection of PFET silicide... In-line voltage contrast detection of PFET silicide...

2009-05-26

2011-10-18

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S797000, C257SE21521, C257SE21524, C324S762010, C324S762100

Reexamination Certificate

active

08039837

ABSTRACT:
A semiconductor test structure includes a PFET transistor, having a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact. The source region and drain region float, and the body contact is electrically connected to the body of the PFET transistor and to the ground. This grounds the body of the PFET transistor, and the body contact of the test structure is electrically connected to a capacitor that is electrically connected to ground.

REFERENCES:
patent: 7456636 (2008-11-01), Patterson et al.
patent: 2007/0221990 (2007-09-01), Cote et al.
patent: 2007/0222470 (2007-09-01), Patterson et al.
patent: 2007/0257317 (2007-11-01), Fechner et al.
patent: 2008/0217612 (2008-09-01), Patterson et al.

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