Improved logic cell array using CMOS E.sup.2 PROM cells

Details Improved logic cell array using CMOS E.sup.2 PROM cells Improved logic cell array using CMOS E.sup.2 PROM cells

1987-08-19

1989-12-05

Gossage, Glenn A.

Static information storage and retrieval

Systems using particular element

Semiconductive

365185, 36518908, 307469, 34082583, 34082587, 34082591, G11C 1140, H03K 19094, H04Q 0000

Patent

active

048857190

ABSTRACT:
A programmable memory cell useful in a logic cell array draws no D.C. power in either a "1" or a "0" state. The cell includes a CMOS transistor pair including a p-channel transistor connected to a positive voltage source and an n-channel transistor connected to a circuit ground potential. The cell output is connected to a common terminal of the CMOS transistor pair. The CMOS transistor pair has a common floating gate which is selectively charged for programming the cell. In a preferred embodiment, the floating gate comprises a first polycrystalline silicon layer (polysilicon), and capacitive means including a second polysilicon layer spaced from and capacitively coupled with the first polysilicon layer is utilized to selectively applying charge to the common floating gate.

REFERENCES:
patent: 4053798 (1977-10-01), Koike et al.
patent: 4228527 (1980-10-01), Gerber et al.
patent: 4596938 (1986-06-01), Cartwright, Jr.
patent: 4686558 (1987-08-01), Adam
patent: 4710900 (1987-12-01), Higuchi
Landry, "Logic Cell Arrays: High Density, User Programmable ASICs", Technological Horizons, Mar. 1986.

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