Imprint suppression circuit scheme

Details Imprint suppression circuit scheme Imprint suppression circuit scheme

2005-09-27

2005-09-27

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S196000

Reexamination Certificate

active

06950328

ABSTRACT:
A ferroelectric memory array includes a plurality of memory pages each formed of a plurality of ferroelectric memory cells. The ferroelectric memory cells are supplied by common word lines. Status memory cells are connected to each of the plurality of memory pages, each status memory cell stores the status of the memory page to which it is connected. A plurality of sense amplifiers each receives inputs from a pair of bit lines. Each of the bit lines receives inputs from the ferroelectric memory cells of a plurality of the memory pages. The sense amplifiers write back data into the memory cells and status cells in reversed states following read operations.

REFERENCES:
patent: 5707861 (1998-01-01), Sherman et al.
patent: 5991197 (1999-11-01), Ogura et al.

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