Implementing termination with a default signal on a bus line

Details Implementing termination with a default signal on a bus line Implementing termination with a default signal on a bus line

1998-12-23

2004-05-18

Myers, Paul R. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S110000

Reexamination Certificate

active

06738844

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to buses for processor based systems, and more particularly to implementing termination on a bus.
BACKGROUND
Computer systems include a processor, one or more memory devices, and one or more input-output or I/O devices. The processor, the memory devices, and the I/O devices communicate with each other through a bus in the computer system. A bus is a communication link comprising a set of wires or lines connected between the devices listed above. The bus is shared by the devices as they communicate with one another. A bus may also be a set of lines connected between two functional circuits in a single integrated circuit. The bus generally contains a set of control lines and a set of data lines. The control lines carry signals representing requests and acknowledgments and signals to indicate what type of data is on the data lines. The data lines carry data, complex commands, or addresses. A separate set of lines in the bus may be reserved to carry addresses, and these are called address lines. The devices communicate with each other over the bus according to a protocol that governs which devices may use the bus at any one time. The protocol is a set of rules governing communication over the bus that are implemented and enforced by a device that is appointed a bus master. Generally the processor is the bus master, although there may be more than one bus master. Each bus master initiates and controls requests to use the bus.
Two different schemes exist for organizing communication on a bus. A synchronous bus includes a clock pulse in the control lines and is governed by a protocol based on the clock pulse. An asynchronous bus does not rely on a clock pulse to organize communication. Rather, the asynchronous bus is coordinated by a handshaking protocol under which a sender communicates directly with a receiver to transfer data based on a series of mutual agreements. The sender and the receiver exchange a set of handshaking signals over the control lines before, during, and after each data transfer.
Signals are exchanged between the sender and the receiver over the bus in the following manner. The sender includes a driver, typically comprising a tri-state output buffer, connected to each bus line it is to send signals to. Likewise, the receiver typically has a high impedance input buffer such as an inverter connected to each bus line it is to receive signals from. When the sender sends a signal on a particular line it directs the appropriate driver to bring the line to a suitable voltage, either high or low. The receiver detects the signal in the appropriate inverter to complete the communication. A reflection of the signal can take place if the input impedance of the inverter is different from the characteristic impedance of the line. The discontinuity in the impedance causes the reflection. The signal is reflected back and forth along the line and the reflections must dissipate before the signal can be accepted as valid. This slows the operation of the bus and the computer system.
Signal reflection also causes inter-signal interference noise (ISI) on the bus. ISI contributes to timing delay variation which limits the frequency at which a bus can transfer signals. ISI must be substantially reduced in high frequency bus structures.
A conventional method of reducing reflection on a bus line is to damp or dissipate the reflection with a termination connected to the bus line. A termination is a dissipating or damping load, typically a resistive device, which has an impedance that is substantially similar to the characteristic impedance of the line. Two types of termination are used. A source termination comprises an impedance placed in a driver connected to the bus line. A parallel termination comprises impedances placed in a driver and an input buffer so that impedances are placed at both ends of a bus line. While the implementation of termination on a bus has been successful in reducing signal reflection, the implementation itself may cause problems with the operation and performance of the bus.
There remains a need for termination in high frequency bus structures and ways of implementing the termination to avoid the above-mentioned problems. For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention a default signal is driven on to a line, then an information signal is driven on to the line, and the default signal is driven on to the line after the information signal is driven on to the line. Advantages of the present invention will be apparent to one skilled in the art upon an examination of the detailed description of the preferred embodiments.


REFERENCES:
patent: 4016541 (1977-04-01), Delagi et al.
patent: 4573154 (1986-02-01), Nakata et al.
patent: 4701841 (1987-10-01), Goodrich et al.
patent: 4744024 (1988-05-01), Potash et al.
patent: 4825402 (1989-04-01), Jalali
patent: 5056110 (1991-10-01), Fu et al.
patent: 5153459 (1992-10-01), Park et al.
patent: 5247522 (1993-09-01), Reiff
patent: 5305385 (1994-04-01), Schanning et al.
patent: 5307345 (1994-04-01), Lozowick et al.
patent: 5343503 (1994-08-01), Goodrich
patent: 5448591 (1995-09-01), Goodrich
patent: 5467455 (1995-11-01), Gay et al.
patent: 5530377 (1996-06-01), Walls
patent: 5541535 (1996-07-01), Cao et al.
patent: 5578940 (1996-11-01), Dillon et al.
patent: 5663661 (1997-09-01), Dillon et al.
patent: 5729152 (1998-03-01), Leung et al.
patent: 5767695 (1998-06-01), Takekuma et al.
patent: 5809263 (1998-09-01), Farmwald et al.
patent: 5821767 (1998-10-01), Osaka et al.
patent: 5822543 (1998-10-01), Dunn et al.
patent: 5831467 (1998-11-01), Leung et al.
patent: 5881066 (1999-03-01), Lepitre
patent: 5949254 (1999-09-01), Keeth
patent: 6005895 (1999-12-01), Perino et al.
patent: 6026456 (2000-02-01), Ilkbahar
patent: 6051989 (2000-04-01), Walck
patent: 6078978 (2000-06-01), Suh
patent: 6092212 (2000-07-01), Muljono et al.
patent: 6124747 (2000-09-01), Nasu
patent: 6232792 (2001-05-01), Starr
patent: 6265893 (2001-07-01), Bates
patent: 6347350 (2002-02-01), Muljono
patent: 6366129 (2002-04-01), Douglas, III et al.
patent: 51-127602 (1976-11-01), None
Muljono, Harry, “Driving the Last Inbound Signal on a Line in a Bus with a Termination”, Pending U.S., Application Ser. No. 10/047,277, filed Jan. 14, 2002.

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