Implementing power savings in HSS clock-gating circuit

Details Implementing power savings in HSS clock-gating circuit Implementing power savings in HSS clock-gating circuit

2008-12-22

2010-11-30

Tan, Vibol (Department: 2819)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S330000, C713S340000, C713S400000, C326S093000, C716S030000

Reexamination Certificate

active

07844843

ABSTRACT:
A power saving clock-gating method and a power saving clock-gating circuit for implementing power savings in High Speed Serializer-deserializer (HSS) cores, and a design structure on which the subject circuit resides are provided. The power saving clock-gating circuit includes a clock gate signal used to initiate the starting and stopping of the C2clocks. The clock gate signal is applied to a first latch of plurality of current-mode logic latches in a clock gate aligner block, which provides clock gate aligned signal to synchronously start a C2clock generator. A power savings logic circuit generates a power down signal to turn off the plurality of current-mode latches and predefined clock buffers after the C2clocks have been started, and then responsive to a changed state of the clock gate signal to turn on the predefined clock buffers and the plurality of current-mode logic latches to begin another synchronous start operation.

REFERENCES:
patent: 7471333 (2008-12-01), Steimle et al.
patent: 2009/0055668 (2009-02-01), Fernsler et al.
patent: 2009/0193283 (2009-07-01), Blaner et al.
patent: 2009/0217068 (2009-08-01), Fernsler et al.
patent: 2009/0224812 (2009-09-01), Fujisawa
patent: 2009/0267649 (2009-10-01), Saint-Laurent et al.

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