Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2002-06-20
2004-11-30
Peyton, Tammara (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S001000, C710S051000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C257S048000, C257S438000, C257S666000, C257S734000, C257S736000, C257S786000
Reexamination Certificate
active
06826637
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is relating to an implementing method for buffering devices, and is more particularly relating to an implementing method for forming buffering devices in one dimension by a tree structure with a dichotomy manner.
2. Description of Related Art
For the integrated circuit (IC) industry, it has been the one with the fastest speed in development and a large growth in the recent years. In the technology, the function of the semiconductor device is also greatly developed and changed day by day. In this situation, it is strongly needed to improve the integration and the multiple functions for the electronic devices. The integrated circuit is the device absolutely needed in the various new products, which are continuously presented in the market. Therefore, the integrated circuit industry can be considered as the most promising star as a high tech industry in the future.
In the current status, during the designing stage on the integrated circuit, it will use some electronic design automation (EDA) tools, so as to help the designing engineers to perform the steps of device placement and the circuit routing. When the EDA tools is used to optimize the design of the circuit layout on the chip, the conditions needed to be considered including the connection relation between the device cells and the path delay. However, the path delay considered by the usual design tool includes only the effect of gate delay, but not includes the effect of interconnect delay. But, since the path delay of the signals in the deep sub-micron chip is resulting from the interconnect delay for the most of cases, and then the EDA tools cannot optimize the circuit design for the deep sub-micron chip.
Referring to
FIG. 1
, it is a drawing, schematically illustrating a circuit layout as a combining result from using an EDA tool. As shown in
FIG. 1
, a chip
100
is formed with a number of output bond pads
110
,
120
,
130
,
140
,
150
,
160
,
170
, and
180
, a signal source root R, and a number of buffers B
1
, B
2
, B
3
, B
4
, B
5
, and B
6
. It has the equal distance between the adjacent output bonding pads. Since the signal generated at the signal source root R is necessary to be transmitted to the output bonding pads
110
,
120
,
130
,
140
,
150
,
160
,
170
, and
180
at the same time, it needs the buffers B
1
, B
2
, B
3
, B
4
, B
5
, and B
6
to amplify the output signal exported from the source root R. As a result, the amplified output signal can drive a number of output bonding pads. If the output signal exported from the signal source root R to the output bonding pads
110
,
120
,
130
,
140
,
150
,
160
,
170
, and
180
is a clock signal, and the clock signal is a signal with a feature of synchronous need. The feature of synchronous need means that it is necessary to have the same arriving time for the clock signal exported from the signal source root R and arriving to the output bonding pads
110
,
120
,
130
,
140
,
150
,
160
,
170
, and
180
through the buffers B
1
, B
2
, B
3
, B
4
, B
5
, and B
6
.
The output bonding pad
110
and the output bonding pad
180
are taken as an example. When the clock signal exported from the signal source root R to the output bonding pad
110
, the clock signal goes through the connection path from the path P
1
, the path P
2
, and the path P
3
. Also and, the clock signal has an interconnection time delay by T
1
for being exported to the output bonding pad
110
. However, when the clock signal exported from the signal source root R to the output bonding pad
180
, the clock signal goes through the connection path from the path P
4
, the path P
5
, and the path P
6
. Also and, the clock signal has an interconnection time delay by T
2
for being exported to the output bonding pad
180
. Since the inside of the chip already has areas that are placed with blocks of other circuits, the placement of the buffers is usually restricted. As a result, the lengths of total path for the clock signals exported from the signal source root R and respectively reaching to the output bonding pad
110
and the output bonding pad
180
are not the same. In other words, the total path length going through the path P
1
, the path P
2
, and the path P
3
is not equal to the total path length through the path P
4
, the path P
5
, and the path P
6
. In this situation, the interconnection time delay for the clock signals going through the two path are therefore not equal, T
1
≠T
2
. Also therefore, the clock signals exported from the signal source root R cannot arrive to the output bonding pad
110
and the output bonding pad
180
at the same time. With the same reasons, the interconnection time delays for the clock signals exported from the signal source root R to the other output bonding pads are also different in connection time. Therefore, according to the example shown in
FIG. 1
, it cannot achieve the feature of synchronous need for the clock signal by only using the EDA tool to assemble the circuit chips.
In order to solve the foregoing issues, the current method is that after the EDA toot is used to assemble the circuit, a test procedure is then performed afterward to check whether or not the signal satisfies the feature of synchronous need. If it is not, an adjustment is performed. After that, jobs of the test procedure and adjustment are repeatedly performed until the signal satisfies the requirement of the synchronous need. As shown in
FIG. 1
, in a general situation, the engineer usually needs to adjust the locations of a number of the buffers, so as to satisfy the features of the synchronous need for the clock signals. Since the locations of the buffers on the chip are arranged in two dimensions, their location can be arranged along with the X-axis or the Y-axis. It is then very high complex and time consuming for the job in considering the various options for positioning the buffers and computing the total length of the connection path from each one of the buffers to the signal source root and the output bonding pads. Further still, the adjustment manner is performed by engineer's operation. Therefore, it would take a long time to repeatedly perform the test procedure and the adjustment. However, the lifetime of the products in the industry of the integrated circuit design is short. Since the product variation in the market is fast and the competition is also strong, the current method in developing the new product is therefore taking long time. This situation would not only increase the cost of research and development but also decrease the timely effectiveness and the competition.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide an implementing method for a number of buffering devices, so that signals can arrive at the output bonding pads with a feature of synchronous need. It can further prevent the unnecessary job of adjustment and test in the circuit design from being repeatedly performed, so as to reduce the need of time to design the integrated circuit and the cost of researching and developing.
In accordance with the foregoing and other objectives of the present invention, an implementing method for a number of buffering device is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the N
th
layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding buffering device for the N
th
layer, respectively. (b) One buffering device for the N+1
th
layer is implemented at a location close to the middle place between two buffering devices for the N
th
layer, and each one of the buffering devices for the N
th
layer is electrically connected to the corresponding one of the buffering devices for the N&pl
Chang Yung-Chung
Chiu You-Ming
Peyton Tammara
Rabin & Berdo P.C.
Via Technologies Inc.
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