Implementing FIFOs in shared memory using linked lists and...

Details Implementing FIFOs in shared memory using linked lists and... Implementing FIFOs in shared memory using linked lists and...

2004-05-21

2009-06-30

Portka, Gary J (Department: 2188)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C711S202000

Reexamination Certificate

active

07555579

ABSTRACT:
FIFOs may be implemented in shared memory using linked lists and interleaved linked lists such that any individual FIFO can dynamically use any free memory location. The system may be implemented in hardware efficiently and does not pre-allocate memory to any FIFO, so that the whole shared memory may be used by any one of the FIFOs. The maximum physical size of a FIFO is then limited only by the size of the physical memory and not by the number of FIFOs sharing the same physical memory or by any mechanism for pre-allocating physical memory to the FIFOs. The linked lists contain data words, each data word containing a data field and a reference to a subsequent free memory location. A subsequent data word may be enqueued to the FIFO at the last referenced free memory location. A dequeue operation returns free memory locations to the free memory pool. Multiple linked lists may be interleaved to accelerate reading of data words from the FIFO.

REFERENCES:
patent: 6754742 (2004-06-01), Alowersson et al.
patent: 6754744 (2004-06-01), Kim et al.
patent: 6760795 (2004-07-01), Goudie et al.
patent: 6888848 (2005-05-01), Beshai et al.
patent: 7342934 (2008-03-01), Mott et al.

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