Implementing enhanced SRAM stability and enhanced chip yield...

Details Implementing enhanced SRAM stability and enhanced chip yield... Implementing enhanced SRAM stability and enhanced chip yield...

2011-03-22

2011-03-22

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S230060, C365S189110, C365S201000, C365S230080, C365S189050

Reexamination Certificate

active

07911827

ABSTRACT:
An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.

REFERENCES:
patent: 2007/0030741 (2007-02-01), Nii et al.
patent: 2008/0253172 (2008-10-01), Yamagami

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