Implementing enhanced SRAM read performance sort ring...

Details Implementing enhanced SRAM read performance sort ring... Implementing enhanced SRAM read performance sort ring...

2007-10-17

2009-10-27

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S190000

Reexamination Certificate

active

07609542

ABSTRACT:
A method and apparatus including a static random access memory (SRAM) cell implement an enhanced SRAM read performance sort ring oscillator (PSRO), and a design structure on which the subject circuit resides is provided. A pair of parallel reverse polarity connected inverters defines a static latch or cross-coupled memory cell. The SRAM cell includes independent left and right wordlines providing a respective gate input to a pair of access transistors used to access to the memory cell. The SRAM cell includes a voltage supply connection to one side of the static latch. For example, a complement side of the static latch is connected to the voltage supply. A plurality of the SRAM cells is assembled together to form a SRAM base block. A plurality of the SRAM base blocks is connected together to form the SRAM read PSRO.

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